Homework5.11

# Homework5.11 - 1.7 times the current per width as p-channel...

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ECE 124d/256c Homework 5 Due: Wed Feb 9, 2011 Reading: DSE Chapter 4, CPL and Flip/Flop Opt papers 1. Design a schematic and stick layout for the following cmos complex gates: a. f= ab+ac+ad+bc+bd+cd where arrival order is: a, b, c, d b. f=ad+ace+be+dcb where arrival is b, (a,c,e), and finally d. (note: static gate can be done in 10 transistors-- not series-parallel). c. Size the transistors for the circuits above so that rise and fall times are roughly equal, with the smallest transistor having an assumed relative size of 1. (Here you may assume that n-channel has
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Unformatted text preview: 1.7 times the current per width as p-channel, both having minimum length). 2. Do problem 1a using CPL gates, Domino CMOS and DCFL. 3. Calculate the proper CMOS driver size to source terminate a center driven 90 ohm transmission line with open terminations at its ends, using 1.8V 180nm technology. Show that the line is indeed terminated, despite being driven from the center, by superposing the reflections and transmissions at the center. DSE p. 216 Problems 4-2, 4-3 2nS 90...
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## This note was uploaded on 12/28/2011 for the course ECE 124d taught by Professor Staff during the Fall '08 term at UCSB.

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