Unformatted text preview: case power rise and fall times of 1.5A/nS. The chip is subject to peak current loads of 9A, and minimal loads of 3A and operates nominally at 1.2V supply. a. If the chip is bumped onto a package with 250pH series inductance on the power and ground connections, how much on-package bypass is needed to hold a voltage tolerance of 10% at 1.2V, assuming ideal supply on the board. If the package is decoupled with chip caps that have no series resistance and 0.7nH series inductance each, find the cap size to minimize the number of parallel caps of a single size needed to do this. b. Now, if the actual board supply bandwidth is 50kHz, how much board decoupling is needed to hold 5% voltage tolerance on the inputs to the chip package? p. 298 6.1, 6.2, 6.3, 6.7...
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This note was uploaded on 12/28/2011 for the course ECE 124d taught by Professor Staff during the Fall '08 term at UCSB.
- Fall '08