Homework7.11 - case power rise and fall times of 1.5A/nS...

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ECE 124d Homework 7 Due: Wed Mar 2, 2011 Reading: Finish Chapter 5 Read Chapter 6 “Noise” 1. Consider a small processor with a 2.5V, 80-bit DDR communication bus operating at 366MHz (1.0 nS rise and fall times). a. If this bus is driving 60 lines on a PC-board, what is the worst case dI/dt if all lines switch at once? b. Assuming that the power to drive the board comes from off chip, what is the maximum allow- able inductance of the power and ground supplies to the chip to limit the voltage drop and ground bounce to 0.25V? How many power/ground bumps will this require at 0.5 nH/bump? c. Assuming activity on the bus 15% of the time on average, with source termination (i.e. no DC power) estimate the average power to drive the DDR bus. 2. Consider a chip with sufficient on chip decoupling and package inductance that it has worst
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Unformatted text preview: case power rise and fall times of 1.5A/nS. The chip is subject to peak current loads of 9A, and minimal loads of 3A and operates nominally at 1.2V supply. a. If the chip is bumped onto a package with 250pH series inductance on the power and ground connections, how much on-package bypass is needed to hold a voltage tolerance of 10% at 1.2V, assuming ideal supply on the board. If the package is decoupled with chip caps that have no series resistance and 0.7nH series inductance each, find the cap size to minimize the number of parallel caps of a single size needed to do this. b. Now, if the actual board supply bandwidth is 50kHz, how much board decoupling is needed to hold 5% voltage tolerance on the inputs to the chip package? p. 298 6.1, 6.2, 6.3, 6.7...
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