lab_final11 - ECE 124d/256c Final Lab: Clock Distribution...

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ECE 124d/256c Final Lab: “Clock Distribution Network” Due: Wednesday March 16, 2011, noon via email to the TA, cc In this lab, your job is to design a single phase 400MHz clock tree suitable for driving 200,000 flip-flops which are uniformly distributed over a L-shaped region of a die as shown in the figure above. Each MMI_FFB flip-flop (clock network leaves) loads its clock input and your clock needs to have a single source which you can assume has zero jitter and is modeled by a single MMI_BUFE gate driven by your (perfect) clock (use a 60pS rise and fall voltage source for the input to this driver). You are using metal interconnect with a resistance of 45m /sq., 40 aF/ μ m 2 area capacitance and 65 aF/ μ m fringing capacitance on each side. The total cap = area component + 2 times the fringe compo- nent. (This specification is so you can make the wire wider and have a reasonable estimation of the capaci- tance and resistance. You may make the wires as long and wide as you desire with any topology you desire). In most cases, a 3 resistor+ 2 capacitor pi-model is sufficient to model the wire segments, however, if you use very wide wires with large currents, you should add appropriate inductors to your model. You need the delivered clock rise time to be less than 200pS at the flip-flops and the maximum skew+jitter must be less than 400pS for both rising and falling edges. Note that the clock delay could be larger than
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This note was uploaded on 12/28/2011 for the course ECE 124d taught by Professor Staff during the Fall '08 term at UCSB.

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lab_final11 - ECE 124d/256c Final Lab: Clock Distribution...

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