lab1b.11

lab1b.11 - ECE 124d/256c Lab1 (part b) Due: Wed Jan. 19,...

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ECE 124d/256c Lab1 (part b) Due: Wed Jan. 19, 2011 (1 week) In this lab, we will explore the coupling of CMOS inverters as drivers and receivers for transmis- sion lines. For this lab, we will use the PTM synthetic models which are academic mock-ups that do not require NDA signatures for release. You will also need the PC-board wire models you de- signed for lab1 part a. Exp1: First, you will need to characterize the driver characteristics and loaded inverter behavior. We will assume that your drivers are built out of thin oxide transistors for this exercise -- in practice, you’d likely use thick oxide ones for higher driver voltages, so we’ll drive the interface at 1.8V for the standard 0.18um devices. Construct a CMOS inverter with 0.18x36um n-channel and 0.18x48um p-channel transistors. Be sure to include appropriate source and drain area and perimeter figures using the minimal sdd=0.48um. (sdd describes the minimum thickness of a contacted source or drain region -- the width is set by the transistor width). In fact, the device will most likely resemble the picture be- low:
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In practice, all the gates are tied together and source/drain regions alternate to get a dense, paral- lel-transistor layout. The end extension is sdd=0.48um and the inter-gate distance is 0.54um. This arrangement is called a matrix transistor and the above parallel transistor has a total width of
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This note was uploaded on 12/28/2011 for the course ECE 124d taught by Professor Staff during the Fall '08 term at UCSB.

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lab1b.11 - ECE 124d/256c Lab1 (part b) Due: Wed Jan. 19,...

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