lab3.11

lab3.11 - ECE 124d/256c Lab 3 In this lab you are to...

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ECE 124d/256c Lab 3 In this lab you are to characterize the behavior of two cells: 1. a classical flip-flop design (the MMI_FFB.sp design from the /eci/tech/tsmc18/tech18/mmi18/stdcell/extract directory) and 2. a classical buffer -- specially wired allow you to determine its value as a parasitic bypass capacitor. Part 1 FF: Flip-flops are tricky circuits to fully characterize, in particular, you need to determine the setup and hold time (i.e. the timing aperture) the clock to q and clock to change times. All of these times are state dependent so need to be found separately for both rising and falling transitions. To make matters more complicated, you typically need to have some idea of the input slew rates to evaluate the jitter in these circuits. a. In this part, use 3 ‘A’ drive inverters to get fast but realistic drives and loads; One each on the d and clock inputs and one loading the q output. Drive the clock and D inputs with two periodic near-square logic signals at 500MHz and at 501 MHz respectively. Choose rise and fall times to
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This note was uploaded on 12/28/2011 for the course ECE 124d taught by Professor Staff during the Fall '08 term at UCSB.

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lab3.11 - ECE 124d/256c Lab 3 In this lab you are to...

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