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Unformatted text preview: ECE 124d/256c Lab 5: Power Bypass Design One week. In this lab, it is you against the power coupled noise. You have a set of capacitors to use on the package and you need to find a bypass solution that keeps the power noise below 10% on each power rail over the relevant time period. Your capacitors can be selected from the follow- ing varieties. Note that for the smaller types, the cost is solely dependent on the packaging option, as is the inductance. You also have the option of adding on-chip bypass area capacitance. Because of package pad issues, you get 70nF on chip for free, but adding additional on-chip bypass adds to the chip area and thus reduces the number of die you get from a wafer. For this chip, an additional 10nF uses 5mm 2 , adding to the 65mm 2 minimum. In the minimum size, you get 654 die per $1,500 wafer. Adding to the area, you get proportionally fewer chips -- but the wafer cost is fixed so your price per chip goes up. This chip is packaged in an epoxy package with a cost of $4 each in large quan-per chip goes up....
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This note was uploaded on 12/28/2011 for the course ECE 124d taught by Professor Staff during the Fall '08 term at UCSB.
- Fall '08