04_HJ_Ch04_p6

04_HJ_Ch04_p6 - 4-1 Chapter 4Processor Design 4-2 Chapter...

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Page 1 4-1 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Chapter 4: Processor Design Topics 4.1 The Design Process 4.2 A 1-Bus Microarchitecture for the SRC 4.3 Data Path Implementation 4.4 Logic Design for the 1-Bus SRC 4.5 The Control Unit 4.6 The 2- and 3-Bus Processor Designs 4.7 The Machine Reset 4.8 Machine Exceptions 4-2 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Block Diagram of 1-Bus SRC 4-3 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan High-Level View of the 1-Bus SRC Design 12 ADD SUB AND OR SHR SHRA SHL SHC NOT NEG C=B INC4 4-4 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan ± One bus connecting most registers allows many different RTs, but only one at a time ± Memory address must be copied into MA by CPU ± Memory data written from or read into MD ± First ALU operand always in A, result goes to C ± Second ALU operand always comes from bus ± Information only goes into IR and MA from bus ± A decoder (not shown) interprets contents of IR ± MA supplies address to memory, not to CPU bus Constraints Imposed by the Microarchitecture ALU C C A 31. 0 32 31 0 0 R0 R31 31 IR MA To memory subsystem MD PC AB 32 32-bit general purpose registers 4-5 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Abstract and Concrete RTN for SRC add Instruction Abstract RTN: (IR M[PC]: PC PC + 4; instruction_execution); instruction_execution := ( • • • add (:= op= 12) R[ra] R[rb] + R[rc]: Step RTN T0 MA PC: C PC + 4; T1 MD M[MA]: PC C; T2 IR MD; T3 A R[rb]; T4 C A + R[rc]; T5 R[ra] C; Concrete RTN for the add instruction ± Parts of 2 RTs (IR M[PC]: PC PC + 4;) done in T0 ± Single add RT takes 3 concrete RTs (T3, T4, T5) IF IEx. ALU C C A 31. 0 32 31 0 0 R0 R31 31 IR MA To memory subsystem MD PC 32 32-bit general purpose registers 4-6 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Concrete RTN Gives Information About Sub-units ± The ALU must be able to add two 32-bit values ± ALU must also be able to increment B input by 4 ± Memory read must use address from MA and return data to MD ± Two RTs separated by : in the concrete RTN, as in T0 and T1, are operations at the same clock ± Steps T0, T1, and T2 constitute instruction fetch, and will be the same for all instructions ± With this implementation, fetch and execute of the add instruction takes 6 clock cycles
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Page 2 4-7 Chapter 4—Processor Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Concrete RTN for Arithmetic Instructions: addi ± Differs from add only in step T4 ± Establishes requirement for sign extend hardware
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This note was uploaded on 12/28/2011 for the course ECE 152b taught by Professor Staff during the Fall '08 term at UCSB.

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04_HJ_Ch04_p6 - 4-1 Chapter 4Processor Design 4-2 Chapter...

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