05_timing_clocking_p2

05_timing_clocking_p2 - TC ECE152B 1 Issues on Timing and...

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ECE152B TC 1 Issues on Timing and Clocking Combinational Logi X Z FF FF Logic QD FF ECE152B TC 2 FF . . . clock clock period clock
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Latch and Flip-Flop D Q L DQ CK Q Q CK L 1 Q L 2 Q Q1 Q2 ECE152B TC 3 D Q CK D Q CK CK D 1 Clocking Combinational Logic X Z For correct operation of a synchronous circuit: FF FF QD FF The clock period must be longer than the delay of the longest path in the combinational logic. The width of the clock pulse must be long enough ECE152B TC 4 clock clock period FF . . . clock to allow the flip-flops to change state.
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Flip-Flop Setup and Hold Times Flip-flop setup time T su : the required time the data input signal value must be held stable prior to the arrival of clock pulse 50% Input date 50% 50% Setup time Hold time clk Input FF DQ clk Q arrival of clock pulse. ECE152B TC 5 z Flip-flop hold time T h : the required time the data input signal value must be held stable after the arrival of clock pulse. Flip-flip Timing Parameters Clk D Clk t hold T ECE152B TC 6 Q t c-q t su Delays can be different for rising and falling data transitions
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Example: For the circuit shown below, assume the delay through the register (t pd ) is 0.6 and the delay through each logic block is indicated inside the box. Assume that the registers, which are positive edge- triggered have a se -up time T of 0 4 What is the triggered, have a set up time T su of 0.4. What is the minimum clock period? logic t pd =5 logic t pd =2 logic t pd =2 register register ECE152B TC 7 Clock θ logic t pd =3 logic t pd =5 t θ t θ A Simple RC Model for Logic Gates equivalen G A B A B a buffer/gate equivalent circuit G C input R out ECE152B TC 8
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Interconnect Models C 1 C 2 driver C 3 1. Ignoring interconnects 2. Lumped capacitance model ECE152B TC 9 3. RC tree model 4. RLC tree model 5. Transmission line models (RC, LC, RLC) 6. RC / RLC Network model Interconnect Models as a Capacitor 1. Ignoring Interconnects: 2. Lumped Capacitance model: R d V out R d V out C output C input C 1 + C 2 + C 3 10 ±x V V OUT C output C input C 1 + C 2 + C 3 + C wire V out (t) = V DD (1 – e –t/T ) T = Rd ( C output +C 1 + C 2 + C 3 ) ECE152B TC 10 1.0 x DD T 2T time 0.5 x V DD or T = Rd ( C output 1 + C 2 + C 3 + C wire ) V out -1 (0.5V DD ) = (ln 2) T = 0.693 T V out (T) = 0.632 V DD
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Analysis of Simple RC Circuit R i(t) ) ( ) ( ) ( ) ( )) ( ( ) ( ) ( ) ( ) ( t v t v dt t dv RC dt t dv C dt t Cv d t i t v t v t i R T T = + = = = + first-order linear differential equation ± v(t) C v T (t) ECE152B TC 11 with constant coefficients state variable Input waveform Analysis of Simple RC Circuit 0 ) ( ) ( = + t v dt t dv RC Zero-input response: (natural response) RC t N Ke (t) v RC dt dv(t) v(t) = = 1 1 Step-input response: match initial state: v 0 v 0 u(t) ) ( ) ( ) ( 0 t u v t v dt t dv RC = + ) ( ) ( ) ( ) ( 0 0 t u v Ke t v t u v t v RC t F + = = 0 ) ( 0 ) 0 ( 0 = + = t u v K v ECE152B TC 12 output response for step-input: v 0 (1-e -t/RC )u(t) ) ( ) 1 ( ) ( 0 t u e v t v RC t = You can get the same result by Laplace Transform
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Delays of Simple RC Circuit v(t) = v 0 (1 - e -t/RC ) -- waveform under step input v 0 u(t) v(t)=0.5v 0 t = 0.7RC – i.e., delay = 0.7RC (50% delay) v(t)=0.1v 0 t = 0.1RC v(t)=0.9v 0 t = 2.3RC – i.e., rise time = 2.2RC Rise time (Fall time): time for a waveform to rise from ECE152B TC 13
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05_timing_clocking_p2 - TC ECE152B 1 Issues on Timing and...

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