05_timing_clocking_p6

05_timing_clocking_p6 - Issues on Timing and Clocking X Z...

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ECE152B TC 1 Issues on Timing and Clocking FF Combinational Logic X Z Q D ECE152B TC 2 FF FF . . . FF clock clock period clock Latch and Flip-Flop D Q Q L DQ Q CK ECE152B TC 3 CK L 1 D Q Q CK L 2 D Q Q CK CK D 1 Q1 Q2 Clocking FF Combinational Logic X Z QD For correct operation of a synchronous circuit: The clock period must be longer than the delay of the longest path in the ECE152B TC 4 clock clock period FF FF . . . FF clock combinational logic. The width of the clock pulse must be long enough to allow the flip-flops to change state. Flip-Flop Setup and Hold Times 50% Input date 50% clk FF Flip-flop setup time T su : the required time the data input signal value must be held stable prior to the arrival of clock pulse. ECE152B TC 5 50% Setup time Hold time Input clk Q z Flip-flop hold time T h : the required time the data input signal value must be held stable after the arrival of clock pulse. Flip-flip Timing Parameters D Clk Q T ECE152B TC 6 D Q Clk t c-q t hold t su Delays can be different for rising and falling data transitions
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Example: For the circuit shown below, assume the delay through the register (t pd ) is 0.6 and the delay through each logic block is indicated inside the box. Assume that the registers, which are positive edge- triggered, have a set-up time T su of 0.4. What is the minimum clock period? logic ECE152B TC 7 Clock θ t pd =5 logic t pd =2 logic t pd =2 logic t pd =3 logic t pd =5 register register t θ t θ A Simple RC Model for Logic Gates A B A B equivalent circuit G G C R out ECE152B TC 8 a buffer/gate input Interconnect Models driver C 1 C 2 C 3 ECE152B TC 9 1. Ignoring interconnects 2. Lumped capacitance model 3. RC tree model 4. RLC tree model 5. Transmission line models (RC, LC, RLC) 6. RC / RLC Network model Interconnect Models as a Capacitor 1. Ignoring Interconnects: 2. Lumped Capacitance model: R d C output C input C 1 + C 2 + C 3 V out R d C output C input C 1 + C 2 + C 3 + C wire V out ECE152B TC 10 1.0 x V DD V OUT T 2T time 0.5 x V DD V out (t) = V DD (1 – e –t/T ) T = Rd ( C output +C 1 + C 2 + C 3 ) or T = Rd ( C output 1 + C 2 + C 3 + C wire ) V out -1 (0.5V DD ) = (ln 2) T = 0.693 T V out (T) = 0.632 V DD Analysis of Simple RC Circuit ) ( )) ( ( ) ( ) ( ) ( ) ( dt t dv C dt t Cv d t i t v t v t i R T = = = + ± v(t) C R v T (t) i(t) ECE152B TC 11 ) ( ) ( ) ( t v t v dt t dv RC T = + first-order linear differential equation with constant coefficients state variable Input waveform Analysis of Simple RC Circuit 0 ) ( ) ( = + t v dt t dv RC Zero-input response: (natural response) Step-input response: RC t N Ke (t) v RC dt dv(t) v(t) = = 1 1 ) ( ) ( ) ( 0 t u v t v dt t dv RC = + RC t ECE152B TC 12 match initial state: output response for step-input: v 0 v 0 u(t) v 0 (1-e -t/RC )u(t) ) ( ) ( ) ( ) ( 0 0 t u v Ke t v t u v t v F + = = ) ( ) 1 ( ) ( 0 t u e v t v RC t = 0 ) ( 0 ) 0 ( 0 = + = t u v K v You can get the same result by Laplace Transform
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Delays of Simple RC Circuit v(t) = v 0 (1 - e -t/RC ) -- waveform under step input v 0 u(t) v(t)=0.5v 0 t = 0.7RC – i.e., delay = 0.7RC (50% delay) v(t)=0.1v 0 t = 0.1RC v(t)=0 9v t = 2 3RC ECE152B TC 13 v(t)=0.9v 0 t = 2.3RC – i.e., rise time = 2.2RC Rise time (Fall time): time for a waveform to rise from 10% to 90%(90% to 10%) of its steady state value V OL V OH Rise time V OL V OH
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This note was uploaded on 12/28/2011 for the course ECE 152b taught by Professor Staff during the Fall '08 term at UCSB.

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05_timing_clocking_p6 - Issues on Timing and Clocking X Z...

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