10_CH07_p2

10_CH07_p2 - 7-1 Chapter 7-Memory System Design Chapter 7:...

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Page 1 7-1 Chapter 7—Memory System Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Chapter 7: Memory System Design Topics 7.1 Introduction: The Components of the Memory System 7.2 RAM Structure: The Logic Designer’s Perspective 7.3 Memory Boards and Modules 7-2 Chapter 7—Memory System Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Fig 7.1 The CPU–Memory Interface Sequence of events: Read: 1. CPU loads MAR, issues Read, and REQUEST 2. Main memory transmits words to MDR 3. Main memory asserts COMPLETE Write: 1. CPU loads MAR and MDR, asserts Write, and REQUEST 2. Value in MDR is written into address in MAR 3. Main memory asserts COMPLETE –more– CPU m Main memory Address bus Data bus s Address 0 1 2 3 2 m –1 A 0 –A m–1 D 0 –D b–1 R/W REQUEST COMPLETE MDR Register file Control signals m w w MAR b
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Page 2 7-3 Chapter 7—Memory System Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Tbl 7.1 Some Memory Properties Symbol Definition Intel Intel PowerPC 8088 8086 601 w CPU word size 16 bits 16 bits 64 bits m Bits in a logical memory address 20 bits 20 bits 32 bits s Bits in smallest addressable unit 8 bits 8 bits 8 bits b Data bus size 8 bits 16 bits 64 bits 2 m Memory word capacity, s-sized wds 2 20 words 2 20 words 2 32 words 2 m xs Memory bit capacity 2 20 x 8 bits 2 20 x 8 bits 2 32 x 8 bits 7-4 Chapter 7—Memory System Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Tbl 7.2 Memory Performance Parameters Symbol Definition Units Meaning t a Access time time Time to access a memory word t c Cycle time time Time from start of access to start of next access k Block size words Number of words per block ω Bandwidth words/time Word transmission rate t l Latency time Time to access first word of a sequence of words t bl = Block time Time to access an entire block of words t l + k/ ω access time (Information is often stored and moved in blocks at the cache and disk level.)
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Page 3 7-5 Chapter 7—Memory System Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Compo- nent Access Random Random Random Direct Sequential Capa- 64-1024+ 8KB-8MB 64MB-2GB 8GB 1TB city, bytes Latency .4-10ns .4-20ns 10-50ns 10ms 10ms-10s Block 1 word 16 words16 words 4KB 4KB size Band- System System 10-4000 50MB/s 1MB/s width clock Clock MB/s Rate rate-80MB/s Cost/MB High $10 $.25 $0.002 $0.01 Table 7.3 The Memory Hierarchy, Cost, and Performance CPU Cache Main Memory Disk Memory Tape Memory Some Typical Values: As of 2003-4. They go out of date immediately. 7-6 Chapter 7—Memory System Design Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Fig 7.3 Conceptual Structure of a Memory Cell Select DataIn DataOut R/W Select DataOut DataIn R/W Regardless of the technology, all RAM memory cells must provide these four functions: Select, DataIn, DataOut, and R/W.
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10_CH07_p2 - 7-1 Chapter 7-Memory System Design Chapter 7:...

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