2011_hw3_solution

2011_hw3_solution - ECE152B HW3 Sample solutions 1. BUS...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE152B HW3 Sample solutions 1. 2 . (a) A B C Arrival time 2 5 3 Required time 3 8 3 Slack 1 3 0 (b) BUS Y in X in Z in Z X Y Z out X out Sel A Sel B A B ALU INC ADD RSH SUB MUX MUX
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
A B C Arrival time 5 10 6 Required time 7 13 6 Slack 2 3 0 (c) Tmin= t c-q + longest_delay+ t su = 12+1+2=15 3. Consider a synchronous circuit with 300 flip flops and a single clock source. We are interested in designing its clock tree. Assume that a buffer with zero load has a propagation delay of 0.25ns. Also assume that a signal with a single fanout (either to a flip flop or to a buffer) has a delay (due to a non zero slew rate) of 0.3ns and the capacitive load of each additional fanout will cause an extra 0.2 ns delay (due to a longer slew rate). a. What is the total delay from the clock source to a flip flop's clock input if only one buffer is used to drive all 300 flip flops in the clock tree.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 3

2011_hw3_solution - ECE152B HW3 Sample solutions 1. BUS...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online