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# hw3 - ECE152B Digital Design Methodologies HW#3(Due Friday...

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Unformatted text preview: ECE152B: Digital Design Methodologies HW #3 (Due: Friday April 22, 2011 at 5pm) 1. (25 pts.) Design a data path that will allow each of the following register transfers to be completed in one clock cycle. There are three 16‐bit registers, X, Y and Z, and one 16‐bit bus, Bus. Use only one ALU. You need to show all required control signals. BUS←Z; Z←BUS; Y←BUS; BUS←X; X←X‐Y; X←X+Y; X←X+1; X←Z‐X; X←Right_Shift(X); 2. (25 pts.) Consider the following circuit for timing analysis. The number inside each box is the propagation delay of the logic block from its input to output. (a) (10 pts.) Derive the arrival time, required time, and slack for each of signals A, B, and C. Ignore the interconnect delays in your analysis (i.e. all interconnects have a zero delay). A B C Arrival time Required time slack (b) (10 pts.) Derive the arrival time, required time, and slack for each of signals A, B, and C with the following assumption of interconnect delays: a single‐fanout interconnect has a delay of 1, and each additional fanout incurs an additional delay of 1. (Note: A, B, and C are at the immediate outputs of the corresponding gates/boxes). A B C Arrival time Required time slack (c) (5 pts.) Now assume PI1, PI2 and PI3 are outputs of flip‐flops and PO1, PO2 and PO3 are inputs of flip‐flops. If the flip‐flop propagation delay tc‐q is 1, setup time tsu is 2, and hold time thold is 3, what is the minimum clock period? Ignore the interconnect delays for this part (i.e. following the same assumption of part (a)). 3. (25 pts.) Consider a synchronous circuit with 300 flip‐flops and a single clock source. We are interested in designing its clock tree. Assume that a buffer with zero load has a propagation delay of 0.25ns. Also assume that a signal with a single fanout (either to a flip‐flop or to a buffer) has a delay (due to a non‐zero slew rate) of 0.3ns and the capacitive load of each additional fanout will cause an extra 0.2 ns delay (due to a longer slew rate). a. What is the total delay from the clock source to a flip‐flop's clock input if only one buffer is used to drive all 300 flip‐flops in the clock tree. b. What is the total delay from the clock source to a flip‐flop's clock input if buffers are used to limit the number of fanouts (to flip‐flops or buffers) to 8. Show your clock tree and the total delay from the source to a flip‐flop's clock input. (Note: the clock source has to be connected to a buffer before being connected to other buffers or flip‐flops.) c. Show a clock tree solution that has a minimum total delay from the clock source to a flip‐flop's clock input (Note: Again, the clock source has to be connected to a buffer before being connected to other buffers or flip‐flops.) ...
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