ECE152B: Digital Design Methodologies
HW #4
(Due: Wednesday May 11, 2011 at 5pm)
1.
(20 pts.) Consider the following circuit. The rectangles represent edge
‐
triggered flip
‐
flops and the circles represent combinational logic. The numbers annotated on the
logic blocks represent the minimum and maximum delays of the blocks. For all the
registers, assume the flip
‐
flop propagation delay is 1, the flip
‐
flop setup time is 0.5
and flip
‐
flop hold time is 0.4. The
δ
's at the clock inputs of the registers represent
the absolute skew between the clock source and the clock port of the register.
a.
(5 pts.) Determine the set of constraints on the clock skew parameters, so that
the circuit works properly (i.e. write down the set of clock
‐
skew constraints
between each pair of registers
Ri
and
Rj
which have direct datapath from
Ri
to
Rj
,
so that the hold
‐
times will not be violated. Specifically, the constraints will be in
the following form:
δ
2
‐
δ
1
≤
X; Y
≤δ
3

δ
2
≤
Z;
δ
4

δ
3
≤
W
‐
you need to find out the
specific values of X, Y, Z and W).
b.
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 Fall '08
 Staff
 4 pts, 10 pts, 15 pts, 7 pts, 5 pt, 4 pt

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