This preview shows page 1. Sign up to view the full content.
Unformatted text preview: 4.4 Extend the SRC instruction set by adding the xor command, (op = 19), which is similar
to the and command, but performs the XOR operation instead of AND. a.Develop the abstract RTN for the xor command. b.Write the concrete RTN and control signals for the xor instruction for the 1bus SRC
microarchitecture. (Unfortunately. the SRC ALU does not have the XOR operation as
one ofits primitives, but only the operations ADD, SUB, AND, OR, SHR, SHL, NEG‘ NOT. C : B. and INC4.)
Solution: 21. xort := op = 19 ) —> R[ra] <— R[rb] XOR R[rc]: b.Using the deﬁnition a xor b = aAb v aaAb cow/mm
—
‘
 p—I 4.7 The SRC instruction set includes the neg instruction, which computes the arithmetic 2’s
complement negation of a register operand. Assume that the NEG operation is not in the
set of operations the ALU can perform. (See page 152.) Develop the concrete RTN and the control sequence to implement the neg instruction for the lbus design. (§4.4) Solution: The NEG instruction can be implemented using the SUB instruction by subtract—
ing the operand from zero to get its negative. Concrete RTN and control sequences for instruction NEG for lbus design follow: Step RTN Control sequence T MA <— PC: C <—— PC + 4; PCOm, MAin, INC4, Cm
MD <— M[MA]: PC <— c; com, PCm, Read. Wait T T . IR <— MD; MDout, 1Rin
. A <— ol; Ain 0
2
3 C <— A — R.[rc]; Grc, Rout', SUB, Cin Rim] 6 TNote: Assume a passive pulldown on the bus, so that it is 0 if no 3—state gates are active. Com, Gra, Rout, End Bus
32 32 4.8 Using Tables 4.6 to 4.1 1, develop as much as you can ofthe control signals MDom, Cm,
and LD. Show both the Boolean equations and the gate—level designs. (§4.5) Solution: MDDUI = T2 + T7ld + Cm = TO + T4{add + addi + 1d) + TGShr + Ld = T4.shr+ T2 T7
Id 4.13 The 2bus SRC design shown in Figure 4.16 allows savings in the number of control
steps to perform an add instruction, but at the expense of additional control hardware.
The text describes the need Io provide additional gate and strobe hardware so that data can be gated from and strobed to the general registers on the Same cycle. Redesign the
hardware shown in Figure 4.4 to accommodate this change. Solution: ﬂaw. 551.3 31 EN '22 2'1 1715 1211 heath: tricth 4.16 Repeat Exercise 4.? for the 2 and 3bus microarchiteetures. (§4.6) Solution: Concrete RTN and control sequences for NEG in a 2bus design: j Control sequence
 Pcout: MAin. C33
 Pcom,1NC4, Pcm, Read, Wait
t MDout! lRins (3:8
Ain
 Grc, Rom, SUB, Sra,Rln,13nd RTN Control sequence
MA 4— PC: MD t— MIMA]: PC MAin, INC4, PCin, Read, Wait
PC *— PC + 4;
IR *— MD; Mom“, 111m, C=B Rm] 5 0* — R[rc]; Grc, Rm", SUB. Sra, Rm, End out ‘ TNote: Assume a passive pulldown on the bus, so that it is 0 if no 3state gates are active. Bus
32 32 ...
View Full
Document
 Fall '08
 Staff

Click to edit the document details