s11_hw4_solution

# s11_hw4_solution - Homework#4 Sample Solutions 1 Consider...

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Unformatted text preview: Homework #4 Sample Solutions: 1. Consider the following circuit. The rectangles represent edge- triggered flip-flops and the circles represent combinational logic. The numbers annotated on the logic blocks represent the minimum and maximum delays of the blocks. For all the registers, assume the flip-flop propagation delay is 1, the flip-flop setup time is 0.5 and flip-flop hold time is 0.4. The 's at the clock inputs of the registers represent the absolute skew between the clock source and the clock port of the register. i. Determine the constraints on the clock skew parameters, so that the circuit works properly. 6 . 18 4 . 18 1 2 1 1 2 min = − + = − + ≤ − h R d p R t t t δ δ 6 . 26 6 . 4 6 . 4 4 . 4 1 6 . 26 4 . 26 1 2 3 2 3 3 2 3 2 2 3 min min ≤ − ≤ − ⇒ ⎪ ⎭ ⎪ ⎬ ⎫ = − + = − + ≤ − = − + = − + ≤ − δ δ δ δ δ δ h R d p R h R d p R t t t t t t 6 . 4 4 . 4 1 4 3 3 4 min = − + = − + ≤ − h R d p R t t t δ δ ii. Derive the constraints that determine the minimum clock period in the presence of skew. ) ( 5 . 21 ) ( 1 2 1 2 2 1 max δ δ δ δ − − = − − + + ≥ s R d p R t t t T ) ( 5 . 28 ) ( 2 3 2 3 3 2 max δ δ δ δ − − = − − + + ≥ s R d p R t t t T ) ( 5 . 6 ) ( 3 2 3 2 2 3 max δ δ δ δ − − = − − + + ≥ s R d p R t t t T ) ( 5 . 6 ) ( 3 4 3 4 4 3 max δ δ δ δ − − = − − + + ≥ s R d p R t t t T iii. Determine the minimum clock period if no clock skew is present. 5 . 28 5 . 6 5 . 6 5 . 28 5 . 21 ) ( ) ( ) ( min 3 4 2 3 1 2 ≥ ⇒ ⎪ ⎪ ⎭ ⎪ ⎪ ⎬ ⎫ ⎪ ⎪ ⎩ ⎪ ⎪ ⎨ ⎧ ≥ ≥ ≥ ≥ ⇒ = − = − = − T T T T T δ δ δ δ δ δ iv. Determine the min. clock period if the clock is routed Determine the min....
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## This note was uploaded on 12/28/2011 for the course ECE 152b taught by Professor Staff during the Fall '08 term at UCSB.

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s11_hw4_solution - Homework#4 Sample Solutions 1 Consider...

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