s11_hw5_solution

s11_hw5_solution - 1. 2. 24 x 24 Multiplier: Delay = 1 + 7...

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1. 2. 24 x 24 Multiplier: Delay = 1 + 7 * Trru + Tadder Ö 1 + 7 * 2 + 2 + 4( log 4 (48) -1 ) Ö 25 gate delays Total # CSA’s = (#CSA / level-1 RRU ) * #level-1 RRU + (#CSA / level-2 RRU ) * #level-2 RRU + (#CSA / level-3 RRU ) * #level-3 RRU + (#CSA / level-4 RRU ) * #level-4 RRU + (#CSA / level-5 RRU ) * #level-5 RRU + (#CSA / level-6 RRU ) * #level-6 RRU + (#CSA / level-7 RRU ) * #level-7 RRU (Note the numbers of CSA’s per RRU are different for RRU at different levels. Here let’s assume:
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#CSA / level-1 RRU ~= 24; #CSA / level-2 RRU ~= 27; #CSA / level-3 RRU ~= 30; #CSA / level-4 RRU ~= 33; #CSA / level-5 RRU ~= 36; #CSA / level-6 RRU ~= 39; #CSA / level-6 RRU ~= 42; Total # CSA’s: Ö 24*8 + 27*5 + 30*3 + 33*2 + 36*2 + 39*1 + 42*1 Ö 636 CSA’s 3. Divide by iterative multiplication We use three registers to store D S , D D and f n . Also assume some tri-state buffers are used to interface the common bus. Step 0:
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This note was uploaded on 12/28/2011 for the course ECE 152b taught by Professor Staff during the Fall '08 term at UCSB.

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s11_hw5_solution - 1. 2. 24 x 24 Multiplier: Delay = 1 + 7...

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