analog_circuit_analysis

analog_circuit_analysis - notes, M. Rodwell, copyrighted...

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notes, M. Rodwell, copyrighted ECE145A / 218A Notes : Basic Analysis of Analog Circuits Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax
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notes, M. Rodwell, copyrighted Comment This (2009) is a transitional year: ext year 145abc will be reorganized Next year 145abc will be reorganized, 145a: fundamentals (devices, analog & RF analysis, models) 145cb: RF systems at IC and system level This year: some students have taken 145c: already have device models already know analog circuit analysis well some students have not must cover device models must review some circuit analysis methods These notes: shortened version (2009 only) of device models
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notes, M. Rodwell, copyrighted Transistor Circuit Design This note set -reviews the basics tarts at the level of a first IC design course -starts at the level of a first IC design course -moves very quickly This will stablish a common terminology -establish a common terminology -accommodate capable students having minimal background in ICs.
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DC models DC bias analysis
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notes, M. Rodwell, copyrighted Large-Signal Model For Bias Analysis I c I b V be + - , 0 that Provided V > sistance itter he o ternal ecified hat ote / where , / and ) / exp( T c b T be s c ce q kT V I I V V I I = = = β resistance emitter the to internal specified is that note ... ex be R V bandwidth. istor peak trans for required near that densities current at operating HBTs for t significan is drop The ex e R I
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notes, M. Rodwell, copyrighted DC Bias Example: Current Mirror ref I 1 Q 2 Q 2 c I ave e 2 ex R 2 ee R 1 ex R 1 ee R 1 e I 2 e I 2 b I 1 b I ) / ln( , ) / ln( and ) ( ) ( have We 2 2 2 1 1 1 2 2 2 2 1 1 1 1 s c t be s c t be ee ex e be ee ex e be I I V V I I V V R R I V R R I V = = + + + + ea) itter he hat sume 2 , 1 that Assume 1 2 ee ee R R = >> β d plies his area). emitter the is ( that assume & 2 1 E E E A A A = 2 / find which we from , 2 and , 2 / implies This 1 2 2 1 2 1 c c s s ex ex I I I I R R = = =
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notes, M. Rodwell, copyrighted Simpler DC Model for Bias Analysis I c I b I c V be I b V be ake stead d ith f ariation the ignore to analysis bias in sufficient often is It . take instead and with of variation , φ on be be c be V V I V bias, bandwidth peak of 10% ~ within densities current at Biased y. technolog and density current upon depends , on be V = HBTs InGaAs/InP V 9 . 0 or 7 . 0 HBTs Si/SiGe Modern V 9 . 0 ~ n e V HBTs GaAs/GaInP V .4 1 , on be
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notes, M. Rodwell, copyrighted Simple DC Bias Example R c I b2 I b1 Q 2 Q 1 R b R ee -V ee b b b b V V V V R I (SiGe). V 9 . 0 e Approximat Volts. 0 then drops, e neglect th we If 2 1 = = = = φ ee ee c c c e e R V V I I I / ) 9 . 0 ( 2 1 2 1 2 1 = = = = + ee ee c c R V V I I 2 / ) 9 . 0 ( 2 1
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notes, M. Rodwell, copyrighted Efficiently Handling Base Currents In Bias Analysis uations multaneo lve n ne t, singifican is drop If b b R I R c here / ) ( 2 : equations us simultaneo solve can one 1 1 2 1 φ ee b b ee c c c R R I V I I I = = + I b2 I b1 Q 2 Q R b , / where 1 1 β c b I I = R ee 1 2 / ) ( solve 1) : iteration by find : Quicker 1 ee ee c R V I = -V 2 / ) ( solve to of value this use 3) / solve 2) 1 1 1 1 ee b b ee c b c b R R I V I I I I = ee
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analog_circuit_analysis - notes, M. Rodwell, copyrighted...

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