aravind_kean_report

aravind_kean_report - Bryan W. Kean Aravind Vijayakumar ECE...

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Bryan W. Kean Aravind Vijayakumar ECE 224A 12/16/04
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Description Our project goal is to implement an analog to digital Delta-Sigma converter that is targeted at a bandwidth from of 20 kHz. A switched capacitor second-order front-end will be used along with a digital filtering scheme on the back end. Changes from Original Specifications The oversampling rate has been reduced from 512 to 256. This was because tones were observed in the noise spectrum at higher OSR’s (Figure 4 vs. Figure 3). This somewhat eases the requirements on the digital filters. On the other hand, the output bit width has been increased substantially to 16 bits. Thus, we intend to stick with the initial proposal of sinc3 decimation by 64 followed by 2 half band filter stages. Some investigation revealed certain half-band structures [1] that are created as cascaded identical sub-filters. The work itself is outside our grasp, but we have a toolbox that lets us design filters of this topology. This essentially reduces the number of coefficients needed by a huge amount. Front End Architecture – System Model The general topology of the front end was analyzed using Simulink. The model was adapted form Brigatti et.al. [2] This allowed us to analyze trade-offs between system specifications, and system variables. In addition to system parameters noise models for kT/C noise, sampling jitter, and amplifier swing constraints (maximum operating voltage, slew rate) were added to the model (Figure 1). With the addition of this a change in the amplifier behavior could be quickly simulated and accounted for before a global spice simulation had to be run. Using this model allowed us to view several problems before actually implementing the circuit, the most notable of which introduced tones for the highest oversampling ratios.
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Figure 1: Simulink model The model above was used to run several simulations with varying operational conditions. A slew rate of 20*10 6 V/s was assumed, and a clock jitter of 1 ns was assumed. Using these specs we were able to achieve 15.6 effective bits, and signal to
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aravind_kean_report - Bryan W. Kean Aravind Vijayakumar ECE...

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