Lecture1

Lecture1 - ECE 224a CMOS VLSI Design Lab F Brewer Digital...

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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology ECE 224a CMOS VLSI Design Lab ECE 224a CMOS VLSI Design Lab F. Brewer
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology ECE 224a ECE 224a Fabricate a real design MMI/Cadence/Mentor/Synopsys Tools MMI Full Custom (Cell, Array, Data-Path) Cadence/Synopsys P&R (digital path) Not a first class in VLSI 124a or equivalent required, 124d is good plan Review Essential Concepts FET, Diode, Transient Model (Elmore), Sizing Layout/Design Rules: Wire Planning, Gradient Variation, Tricks of Trade
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology Class Logistics Class Logistics Homework (out wed, due 1 week) Quizzes (3 in-class) No Final Design Proposal Design Review Submitted Project Report
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology The First Integrated Circuits The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology Intel 4004 Micro-Processor Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology 0.6um 3M 3.3-5V bulk CMOS P1/P2 CAP Poly Resistor HV Implants (up to 40V!) 2.25mm 2 1.5mmx1.5mm 9 week design cycle, 3 person ECE224a Project ECE224a Project
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology Current State of Affairs Current State of Affairs High-End Technology (32-22nm) still a driver Limited to large design efforts ($$$NRE) Small number of Players FPGA: Actel, Lattice, Xilinx, Altera Processor: AMD, Intel, IBM SOC: Conexant, Cisco, Juniper, Nintendo… Structured ASIC: NEC, Fujitsu, Hitatchi, Samsung Most Design Starts > 0.09um! Mixed Signal Applications Mature Technology – Lower NRE and Risk High Potential for Innovative Design/Architecture
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology 224a Project Limits 224a Project Limits Get 1 1.5x1.5mm design/2-3 students 1500 Standard Cell Gates 50kbits ROM/5kbits SRAM 64 Comparators/ 15 Op-Amps 40-48 pins (at least 8 used for Pwr/Gnd) 100Mhz practical large swing (3.3V) limit 800+MHz differential 300mV 3.3 or 5V default, 12V possible
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology Design Schedule Design Schedule 9 week design flow 1 week project definition 3 weeks schematic/simulation + test design 2 weeks layout 2 weeks design verification and tweak Tape Out Must be DRC, LVS Clean Must have Full Die Simulation/Sanity Must have test plan and agree to physical test
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© Digital Integrated Circuits 2nd and F. Brewer 2003, 2011 Design Methodology Survival Guide Survival Guide Choose Team to Complement Skills!
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Lecture1 - ECE 224a CMOS VLSI Design Lab F Brewer Digital...

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