Lecture2

Lecture2 - ECE 224a ECE Process and Design Rules Process...

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EE141 1 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing ECE 224a ECE 224a Process and Design Rules Process and Design Rules Process Overview Device Fabrication Limits Derived Layers Self Alignment/Dual Damascene/CMP Design Rules Resolution/Step Coverage/Process Electrical/Reliability/Mechanical Stress
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EE141 2 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing A Modern CMOS Process A Modern CMOS Process p-well n-well p+ p-epi SiO 2 AlCu poly n+ SiO 2 p+ gate-oxide Tungsten TiSi 2 Dual-Well Trench-Isolated CMOS Process Dual-Well Trench-Isolated CMOS Process
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EE141 3 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing The Manufacturing Process The Manufacturing Process Photo-Lithography Mask to Resist Resist to Pattern Layer Process (Implant/Etch/Oxide/Nitride/…) Cleanup (Clean/Planarization/Anneal) Setup next Layer for Processing For a great reference source: http://www.reed-electronics.com/semiconductor
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EE141 4 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing oxidation optical mask process step photoresist coating photoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process Photo-Lithographic Process
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EE141 5 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing Patterning of SiO2 Patterning of SiO2 Si-substrate Si-substrate Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate Si-substrate Si-substrate SiO 2 SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Hardened resist Chemical or plasma etch
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EE141 6 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing CMOS Process Walk-Through CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)
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EE141 7 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing CMOS Process Walk-Through CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p
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EE141 8 F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits 2nd Manufacturing CMOS Process Walk-Through CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon) (h) After n + source/drain and p + source/drain implants. These p + n + steps also dope the polysilicon.
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This note was uploaded on 12/29/2011 for the course ECE 224a taught by Professor Brewer,f during the Fall '08 term at UCSB.

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Lecture2 - ECE 224a ECE Process and Design Rules Process...

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