Lecture12dram

Lecture12dram - DRAM: Dynamic RAM Store their contents as...

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EE141 1 Memory STMicro/Intel/UCSD/THNU DRAM: Dynamic RAM DRAM: Dynamic RAM Store their contents as charge on a capacitor rather than in a feedback loop. 1T dynamic RAM cell has a transistor and a capacitor
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EE141 2 Memory STMicro/Intel/UCSD/THNU DRAM Read DRAM Read 1. bitline precharged to V DD /2 2. wordline rises, cap. shares it charge with bitline, causing a voltage V 3. read disturbs the cell content at x, so the cell must be rewritten after each read bit cell cell DD C C C V V + = 2
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EE141 3 Memory STMicro/Intel/UCSD/THNU DRAM write DRAM write On a write, the bitline is driven high or low and the voltage is forced to the capacitor
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EE141 4 Memory STMicro/Intel/UCSD/THNU DRAM Array DRAM Array
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EE141 5 Memory STMicro/Intel/UCSD/THNU DRAM DRAM Bitline cap is an order of magnitude larger than the cell, causing very small voltage swing. A sense amplifier is used. Three different bitline architectures, open, folded, and twisted, offer different compromises between noise and area.
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EE141 6 Memory STMicro/Intel/UCSD/THNU DRAM in a nutshell DRAM in a nutshell Based on capacitive (non-regenerative) storage Highest density (Gb/cm2) Large external memory (Gb) or embedded DRAM for image, graphics, multimedia… Needs periodic refresh -> overhead, slower
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EE141 7 Memory STMicro/Intel/UCSD/THNU
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EE141 8 Memory STMicro/Intel/UCSD/THNU Classical DRAM Organization Classical DRAM Organization (square) (square) r o w d e c o d e r row address Column Selector & I/O Circuits Column Address data RAM Cell Array word (row) select bit (data) lines Each intersection represents a 1-T DRAM Cell
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EE141 9 Memory STMicro/Intel/UCSD/THNU DRAM logical DRAM logical organization (4 Mbit) organization (4 Mbit)
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EE141 10 Memory STMicro/Intel/UCSD/THNU DRAM physical organization (4 Mbit,x16) Mbit,x16)
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EE141 11 Memory STMicro/Intel/UCSD/THNU A D OE_L 256K x 8 DRAM 9 8 WE_L Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low Din and Dout are combined (D): WE_L is asserted (Low), OE_L is disasserted (High) D serves as the data input pin WE_L is disasserted (High), OE_L is asserted (Low) D is the data output pin Row and column addresses share the same pins (A) RAS_L goes low: Pins A are latched in as row address CAS_L goes low: Pins A are latched in as column address RAS/CAS edge-sensitive CAS_L RAS_L DRAM DRAM
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EE141 12 Memory STMicro/Intel/UCSD/THNU DRAM Operations DRAM Operations Write Charge bitline HIGH or LOW and set wordline HIGH Read Bit line is precharged to a voltage halfway between HIGH and LOW , and then the word line is set HIGH. Depending on the charge in the cap, the precharged bitline is pulled slightly higher or lower. Sense Amp Detects change Explains why Cap can’t shrink Need to sufficiently drive bitline Increase density => increase parasitic capacitance Word Line Bit Line C Sense Amp .
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This note was uploaded on 12/29/2011 for the course ECE 224a taught by Professor Brewer,f during the Fall '08 term at UCSB.

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Lecture12dram - DRAM: Dynamic RAM Store their contents as...

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