Lecture12sram - Array Structured Memories STMicro/Intel...

EE141
1
Memory
STMicro/Intel/UCSD/THNU
Array Structured Memories
STMicro/Intel
UCSD CAD LAB
Weste Text

EE141
2
Memory
STMicro/Intel/UCSD/THNU
Memory Arrays
Memory Arrays
Memory Arrays
Random Access Memory Serial Access Memory
Content Addressable Memory
(CAM)
Read/Write Memory
(RAM)
(Volatile)
Read Only Memory
(ROM)
(Nonvolatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Shift Registers Queues
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Serial In
Parallel Out
(SIPO)
Parallel In
Serial Out
(PISO)
Mask ROM
Programmable
ROM
(PROM)
Erasable
Programmable
ROM
(EPROM)
Electrically
Erasable
Programmable
ROM
(EEPROM)
Flash ROM

EE141
3
Memory
STMicro/Intel/UCSD/THNU
Feature Comparison
Feature Comparison
Between Memory Types
Between Memory Types

EE141
4
Memory
STMicro/Intel/UCSD/THNU
Array Architecture
Array Architecture

2
n
words of 2
m
bits each

If n >> m, fold by 2
k
into fewer rows of more columns

Good regularity – easy to design

Very high density if good cells are used
row decoder
column
decoder
n
n-k
k
2 m bits
column
circuitry
bitline conditioning
memory cells:
2 n-k rows x
2 m+k columns
bitlines
wordlines

EE141
5
Memory
STMicro/Intel/UCSD/THNU
Memory - Real
Memory - Real
Organization
Organization
S
0
S
R-1
Row
Decoder
Log
2
R
Address
Lines
- - - - K x M bits - - - -
C of M bit words
row 0
C of M bit words
row 1
C of M bit words
row 2
C of M bit words
row N-2
C of M bit words
row N-1
Array of N x K words
------------- columns ------------ KxM
------------- rows
R------------
Log
2
C
Address
Lines
Column Select
M bit data word

EE141
6
Memory
STMicro/Intel/UCSD/THNU
Hierarchical Memory
Architecture
Architecture
Global Data Bus
Row
Address
Column
Address
Block
Address
Block Selector Global
Amplifier/Driver
I/O
Control
Circuitry
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings

EE141
7
Memory
STMicro/Intel/UCSD/THNU
Array Organization Design
Issues
Issues

aspect ratio should be relative square

Row / Column organisation (matrix)

R = log2(N_rows); C = log2(N_columns)

R + C = N (N_address_bits)

number of rows should be power of 2

number of bits in a row need not be…

sense amplifiers to speed voltage swing

1 -> 2
R
row decoder

1 -> 2
C
column decoder

M column decoders (M bits, one per bit)
–
M = output word width

EE141
8
Memory
STMicro/Intel/UCSD/THNU
Simple 4x4 SRAM
Memory
Memory
A
0
Row Decoder
BL
WL[0]
A
1
A
2
Column Decoder
sense amplifiers
write circuitry
!BL
WL[1]
WL[2]
WL[3]
bit line precharge
2 bit width: M=2
R = 2 => N_rows = 2
R
= 4
C = 1
N_columns = 2
c
x M = 4
N = R + C = 3
Array size =
N_rows x N_columns = 16
clocking and
control ->
enable
read
precharge
A 0 !
WE! , OE!

EE141
9
Memory
STMicro/Intel/UCSD/THNU
SRAM Read Timing
SRAM Read Timing
(typical)
(typical)

EE141
10
Memory
STMicro/Intel/UCSD/THNU
SRAM Read Timing
SRAM Read Timing
(typical)
(typical)
stable stable stable
valid valid valid
t t
≥ t
t
t
t
t
Max(t t )
t
ADDR
CS_L
OE_L
DOUT
WE_L = HIGH

EE141
11
Memory
STMicro/Intel/UCSD/THNU
SRAM Architecture and
SRAM Architecture and
Read Timings
Read Timings
tAA
tACS
tOE
tOZ
tOH

EE141
12
Memory
STMicro/Intel/UCSD/THNU
SRAM write cycle timing
SRAM write cycle timing
~WE controlled
~CS controlled