f37-book-intarch-pres-pt2

f37-book-intarch-pres-pt2 - Part II Instruction-Set...

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Jan. 2011 Computer Architecture, Instruction- Slide 1 Part II Instruction-Set Architecture
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Jan. 2011 Computer Architecture, Instruction- Slide 2 About This Presentation This presentation is intended to support the use of the textbook Computer Architecture: From Microprocessors to Supercomputers , Oxford University Press, 2005, ISBN 0-19-515455-X. It is updated regularly by the author as part of his teaching of the upper- division course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara. Instructors can use these slides freely in classroom teaching and for other educational purposes. Any other use is strictly prohibited. © Behrooz Parhami Edition Released Revised Revised Revised Revised First June 2003 July 2004 June 2005 Mar. 2006 Jan. 2007 Jan. 2008 Jan. 2009 Jan. 2011
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Jan. 2011 Computer Architecture, Instruction- Slide 3 A Few Words About Where We Are Headed Performance = 1 / Execution time simplified to 1 / CPU execution time CPU execution time = Instructions × CPI / (Clock rate) Performance = Clock rate / ( Instructions × CPI ) Define an instruction set; make it simple enough to require a small number of cycles and allow high clock rate, but not so simple that we need many instructions, even for very simple tasks (Chap 5-8) Design hardware for CPI = 1; seek improvements with CPI > 1 (Chap 13-14) Design ALU for arithmetic & logic ops (Chap 9-12) Try to achieve CPI = 1 with clock that is as high as that for CPI > 1 designs; is CPI < 1 feasible? (Chap 15-16) Design memory & I/O structures to support ultrahigh-speed CPUs
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Jan. 2011 Computer Architecture, Instruction- Slide 4 Strategies for Speeding Up Instruction Execution Performance = 1 / Execution time simplified to 1 / CPU execution time CPU execution time = Instructions × CPI / (Clock rate) Performance = Clock rate / ( Instructions × CPI ) Items that take longest to inspect dictate the speed of the assembly line Assembly line analogy Single-cycle (CPI = 1) Multicycle (CPI > 1) Parallel processing or pipelining Faster Faster
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Jan. 2011 Computer Architecture, Instruction- Slide 5 II Instruction Set Architecture Topics in This Part Chapter 5 Instructions and Addressing Chapter 6 Procedures and Data Chapter 7 Assembly Language Programs Chapter 8 Instruction Set Variations Introduce machine “words” and its “vocabulary,” learning: A simple, yet realistic and useful instruction set Machine language programs; how they are executed RISC vs CISC instruction-set design philosophy
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Jan. 2011 Computer Architecture, Instruction- Slide 6 5 Instructions and Addressing Topics in This Chapter 5.1 Abstract View of Hardware 5.2 Instruction Formats 5.3 Simple Arithmetic / Logic Instructions 5.4 Load and Store Instructions 5.5 Jump and Branch Instructions 5.6 Addressing Modes First of two chapters on the instruction set of MiniMIPS: Required for hardware concepts in later chapters Not aiming for proficiency in assembler programming
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Jan. 2011 Computer Architecture, Instruction- Slide 7 5.1 Abstract View of Hardware Figure 5.1 Memory and processing subsystems for MiniMIPS.
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This note was uploaded on 12/29/2011 for the course ECE 241 taught by Professor Gibson,j during the Fall '08 term at UCSB.

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f37-book-intarch-pres-pt2 - Part II Instruction-Set...

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