f37-book-intarch-pres-pt5

f37-book-intarch-pres-pt5 - Feb. 2011 Computer...

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Unformatted text preview: Feb. 2011 Computer Architecture, Memory Slide 1 Part V Memory System Design Feb. 2011 Computer Architecture, Memory Slide 2 About This Presentation This presentation is intended to support the use of the textbook Computer Architecture: From Microprocessors to Supercomputers , Oxford University Press, 2005, ISBN 0-19-515455-X. It is updated regularly by the author as part of his teaching of the upper- division course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara. Instructors can use these slides freely in classroom teaching and for other educational purposes. Any other use is strictly prohibited. Behrooz Parhami Edition Released Revised Revised Revised Revised First July 2003 July 2004 July 2005 Mar. 2006 Mar. 2007 Mar. 2008 Feb. 2009 Feb. 2011 Feb. 2011 Computer Architecture, Memory Slide 3 V Memory System Design Topics in This Part Chapter 17 Main Memory Concepts Chapter 18 Cache Memory Organization Chapter 19 Mass Memory Concepts Chapter 20 Virtual Memory and Paging Design problem We want a memory unit that: Can keep up with the CPUs processing speed Has enough capacity for programs and data Is inexpensive, reliable, and energy-efficient Feb. 2011 Computer Architecture, Memory Slide 4 17 Main Memory Concepts Technologies & organizations for computers main memory SRAM (cache), DRAM (main), and flash (nonvolatile) Interleaving & pipelining to get around memory wall Topics in This Chapter 17.1 Memory Structure and SRAM 17.2 DRAM and Refresh Cycles 17.3 Hitting the Memory Wall 17.4 Interleaved and Pipelined Memory 17.5 Nonvolatile Memory 17.6 The Need for a Memory Hierarchy Feb. 2011 Computer Architecture, Memory Slide 5 17.1 Memory Structure and SRAM Fig. 17.1 Conceptual inner structure of a 2 h g SRAM chip and its shorthand representation. / h Write enable / g Data in Address Data out Chip select Q C Q D FF Q C Q D FF Q C Q D FF / g Output enable 1 0 2 1 h Address decoder Storage cells / g / g / g WE CS OE D in D out Addr . . . Feb. 2011 Computer Architecture, Memory Slide 6 Multiple-Chip SRAM Fig. 17.2 Eight 128K 8 SRAM chips forming a 256K 32 memory unit. / WE CS OE D in D out Addr WE CS OE D in D out Addr WE CS OE D in D out Addr WE CS OE D in D out Addr WE CS OE D in D out Addr WE CS OE D in D out Addr WE CS OE D in D out Addr 18 / 17 32 WE CS OE D in D out Addr Data in Data out, byte 3 Data out, byte 2 Data out, byte 1 Data out, byte 0 MSB Address Feb. 2011 Computer Architecture, Memory Slide 7 SRAM with Bidirectional Data Bus Fig. 17.3 When data input and output of an SRAM chip are shared or connected to a bidirectional data bus, output must be disabled during write operations....
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f37-book-intarch-pres-pt5 - Feb. 2011 Computer...

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