f37-book-intarch-pres-pt7

f37-book-intarch-pres-pt7 - Part VII Advanced Architectures...

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Feb. 2011 Computer Architecture, Advanced Architectures Slide 1 Part VII Advanced Architectures
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Feb. 2011 Computer Architecture, Advanced Architectures Slide 2 About This Presentation This presentation is intended to support the use of the textbook Computer Architecture: From Microprocessors to Supercomputers , Oxford University Press, 2005, ISBN 0-19-515455-X. It is updated regularly by the author as part of his teaching of the upper-division course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara. Instructors can use these slides freely in classroom teaching and for other educational purposes. Any other use is strictly prohibited. © Behrooz Parhami Edition Released Revised Revised Revised Revised First July 2003 July 2004 July 2005 Mar. 2007 Feb. 2011* * Minimal update, due to this part not being used for lectures in ECE 154 at UCSB
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Feb. 2011 Computer Architecture, Advanced Architectures Slide 3 VII Advanced Architectures Topics in This Part Chapter 25 Road to Higher Performance Chapter 26 Vector and Array Processing Chapter 27 Shared-Memory Multiprocessing Chapter 28 Distributed Multicomputing Performance enhancement beyond what we have seen: • What else can we do at the instruction execution level? • Data parallelism: vector and array processing • Control parallelism: parallel and distributed processing
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Feb. 2011 Computer Architecture, Advanced Architectures Slide 4 25 Road to Higher Performance Review past, current, and future architectural trends: • General-purpose and special-purpose acceleration • Introduction to data and control parallelism Topics in This Chapter 25.1 Past and Current Performance Trends 25.2 Performance-Driven ISA Extensions 25.3 Instruction-Level Parallelism 25.4 Speculation and Value Prediction 25.5 Special-Purpose Hardware Accelerators 25.6 Vector, Array, and Parallel Processing
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Feb. 2011 Computer Architecture, Advanced Architectures Slide 5 25.1 Past and Current Performance Trends 0.06 MIPS (4-bit processor) Intel 4004: The first μ p (1971) Intel Pentium 4, circa 2005 10,000 MIPS (32-bit processor) 8008 8080 8084 8-bit 8086 80186 80286 16-bit 8088 80188 80386 Pentium, MMX Pentium Pro, II 32-bit 80486 Pentium III, M Celeron
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Feb. 2011 Computer Architecture, Advanced Architectures Slide 6 Architectural Innovations for Improved Performance Architectural method Improvement factor 1. Pipelining (and superpipelining) 3-8 2. Cache memory, 2-3 levels 2-5 3. RISC and related ideas 2-3 4. Multiple instruction issue (superscalar) 2-3 5. ISA extensions (e.g., for multimedia) 1-3 6. Multithreading (super-, hyper-) 2-5 ? 7. Speculation and value prediction 2-3 ? 8. Hardware acceleration 2-10 ? 9. Vector and array processing 2-10 ? 10 . Parallel/distributed computing 2-1000s ? Established methods Newer Previously discussed Covered in Part VII Available computing power ca. 2000: GFLOPS on desktop TFLOPS in supercomputer center PFLOPS on drawing board Computer performance grew by a factor of about 10000 between 1980 and 2000 100 due to faster technology 100 due to better architecture
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Feb. 2011 Computer Architecture, Advanced Architectures Slide 7 Peak Performance of Supercomputers PFLOPS TFLOPS
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f37-book-intarch-pres-pt7 - Part VII Advanced Architectures...

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