MicroBlaze_Overview

MicroBlaze_Overview - MicroBlazeOverview ForrestBrewer Core...

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    MicroBlaze Overview Forrest Brewer
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    Core RISC Architecture 3/5 stage single-issue pipe Separate Data and Ins 32 32-bit GP registers 32-bit instructions 3-operand/2-address modes Optional MMU Optional Busses: LMB (local memory) OPB (on-chip peripheral) PLB (Processor Local Bus) PLB from IBM PowerPC
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    Core Options OPB (Data or Ins) LMB (Data or Ins) PLB (Data or Ins) Divider/Barrel Shifter HW Debug FSL links (Multi-processor) Data and Ins Caches Exception Support FPU HW Floating Point Convert MMU Each option adds to the  processor footprint on the  FPGA Special Registers: MSR (Machine Status) (1) EAR (Exception Address)  (3) ESR (Exception Status) (5) PC (Program Counter) (0) FSR (FPU Status) (7) BTR (Branch Target) (11) All via SPR[x] E.g. PC is SPR[0]
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    Data Layout Word Bit-reversed big-endian Half Word Byte Byte n Byte n+1 Byte n+2 Byte n+3 MSByte LSByte 0 31 MSBit LSBit
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    Instruction Format 3-operand Instructions (5-bit field) 16-bit Immedate Operands Load/Store *(Ra+Rb) and *(Ra+Immediate)
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    GP Registers
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    Processor Version Reg 11 32-bit status registers describing the processor  options and a unique identifier as well as cache sizes  TLB options and target FPGA design. Required because there are dozens of optional  processor components– allowing software to  configure for hardware options
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    3 or 5 state Pipeline Choice of pipeline depth 5-stage offers faster clock, but longer latency Branch requires 3-cycles in the Execution step Delay Slots Like the MIPS design, only flush the fetch on taken branch Decode stage instruction will complete (branch delay slot) Cannot have IMM, branch or break ins in delay slot.
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  • Fall '08
  • Brewer,F
  • data area, Ins Caches Exception, user vector  exception, Hardware Exception NMI, Exception Handler Dispatch

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