2011_HW1_Solution

2011_HW1_Solution - 3.1 (Parallel Gate Evaluation) The...

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p-1 ECE255A HW1 Solution 3.1 (Parallel Gate Evaluation) The Z -to- u conversion, i.e., to convert a signal x = x 1 x 2 to ˆ x = ˆ x 1 ˆ x 2 according to the following rule, 00 => 00 (0 => 0) 01 => 01 ( u => u ) 10 => 01 ( Z => u ) 11 => 11 (1 => 1) can be realized by ˆ x 1 = x 1 x 2 ˆ x 2 = x 1 + x 2 Note that the Z -to -u conversion is necessary only if the gate input is driven by tri-state gate. (a) Apply the Z -to- u conversion, ˆ A 1 = A 1 & A 2 ˆ A 2 = A 1 | A 2 ˆ B 1 = B 1 & B 2 ˆ B 2 = B 1 | B 2 &, |, and ~ denote the bitwise AND, OR, and NOT operations, respectively. AND, OR, and NOT evaluation procedures are as follows. C = AND( A , B ): C 1 = ˆ A 1 & ˆ B 1 C 2 = ˆ A 2 & ˆ B 2 C = OR( A , B ): C 1 = ˆ A 1 | ˆ B 1 C 2 = ˆ A 2 | ˆ B 2 C = NOT( A ) 1 2 2 1 ˆ ~ ˆ ~ A C A C = =
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p-2 ECE255A HW1 Solution (b) Two-to-one multiplexer. Let A and B be the 0/1 inputs, E the selection input, and O the output. O = ˆ A if ˆ E = 0 ˆ B if ˆ E = 1 u if ˆ E = u The k-maps are as follows. O 1 ˆ A 1 ˆ B 1 00 01 11 10 ˆ E 1 ˆ E 2 00 0 0 1 1 01 0 0 0 0 11 0 1 1 0 10 x x x x O 2 ˆ A 2 ˆ B 2 00 01 11 10 ˆ E 1 ˆ E 2 00 0 0 1 1
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This note was uploaded on 12/29/2011 for the course ECE 254b taught by Professor Parhami,b during the Fall '08 term at UCSB.

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2011_HW1_Solution - 3.1 (Parallel Gate Evaluation) The...

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