Solutions_2010Fall_midterm

Solutions_2010Fall_midterm - UNIVERSITY OF CALIFORNIA Santa...

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UNIVERSITY OF CALIFORNIA Santa Barbara Department of Electrical and Computer Engineering ECE255A Fall 2010 MID-TERM EXAMINATION Name: __ Solutions __________________________ PERM: ____________________________ Note: Open book, open notes Problem Number Weight Score 1. 6 _________________ 2. 6 _________________ 3. 10 _________________ 4. 10 _________________ 5. 10 _________________ 6. 10 _________________ 7. 14 __________________ 8. 14 __________________ ___________________________________________________________________ Total 80 __________________
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1. (6 pts.) Is the double-stuck-at fault ( f1 , f2 ) in a combinational circuit detected, undetected, or unknown by a test T , if fault simulation of T for single-stuck-at faults, f1 and f2 , produces the following result? (a) (1 pt) Both f1 and f2 are detected. Your answer: __ unknown ________________ (b) (1 pt) Only f1 is detected. Your answer: ___ unknown ______________________ (c) (1 pt) Neither is detected. Your answer: ___ unknown ______________________ Answer the above questions again if we know f1 is a single-stuck-at fault on a primary output and f2 is a single-stuck-at fault on an internal signal. (a) (1 pt) Both f1 and f2 are detected. Your answer: __ detected ________________ (b) (1 pt) Only f1 is detected. Your answer: ___ detected ______________________ (c) (1 pt) Neither is detected. Your answer: ____ undetected _____________________ 2. (6 pts.) There are two test sequences S1 and S2 for a sequential circuit with 3 primary inputs, each of which has 3 vectors: T1 :{01X, X11, 00X}, T2 ={11X, 011, 01X}. T1 detects fault f1 and T2 detects fault f2 . Try to compact these two sequences into a single sequence with as few vectors as possible which can still guarantee the detection of both faults f1 and f2 . Number of vectors of your resulting sequence: _____ 4 _____________ Your compacted sequence S=__ {11X, 011, 011, 00X }______________ 3. (10 pts.) Consider using the Boolean Satisfibility approach for test generation of a circuit which consists of only one two-input AND gate. The two inputs are
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Solutions_2010Fall_midterm - UNIVERSITY OF CALIFORNIA Santa...

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