mms_intro

mms_intro - ECE-256d Malgorzata Marek-Sadowska...

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Unformatted text preview: ECE-256d Malgorzata Marek-Sadowska MarekElectrical and Computer Engineering Department Engineering I, room 4111 [email protected] 256d 1 CAD for semi-custom ASICs ASIC = application specific integrated circuit ASIC application Semi-Custom = try to design reusing some already Semidesigned parts CAD = flow through a sequence of design steps and CAD software tools. Spectrum of design approaches Fully custom means everything Done by hand, mostly at the transistor and layout level. Example : microprocessors. Semi-custom means try to Semidesign using existing parts. design Example: ethernet chip,hard disk controller. 256d 2 1 Example of modern system-on-a-chip IC system-onMany big chunks Many Random logic RISC CPU Core Memory Datapath 256d 3 Useful Components in Semi-Custom Logic gates Logic Maximally useful components you can reuse Maximally Can design without knowing exactly what gates (type, speed, Can power, size) you have : technology independent design. Later, can map technology independent design onto specific Later, gate library (technology) : technology mapping problem. Memories Memories Module generator transforms specs on size (bits, words, Module speeds) into final layout. Very structured designs. Very Datapaths Datapaths Well structured (adders, multipliers) W ell Often designed at gate and transistor level Often Produced by module generators. Produced 256d 4 2 Semi-custom ASIC SemiMade out of standard cells Made Standard cell = one gate (complex) Random logic RISC CPU Core Memory Datapath 256d 5 ASIC CAD Tool Flow Behavioral synthesis Logic synthesis Technology mapping Verification, test Timing and power estimation Partitioning Row based layout Design rule checking and extraction 256d 6 3 High level (behavioral synthesis) Input : Input High level description of desired system function, usually as High a program in a hardware description language (Verilog, (Verilog, VHDL). Output: Output: Register transfer level structure: FSMs, logic, ALUs, Register FSMs, ALUs, memory, busses. 256d 7 Logic synthesis Input: Input: Boolean equations, state diagrams, etc. Boolean Output: Output: Gates and connections, called netlist, a structural Gates netlist, design. Boolean equations Logic synthesis 256d 8 4 Technology mapping Input: Input: Technology independent gate level design (unTechnology (uncommited design) Output: Output: Gate level design using specific technology library. Gate Technology mapping 256d 9 Formal verification Input: Input: A specification for a design (Boolean eqns) and an specification eqns) implementation Output: Output: Decision yes/no: is specification == implementation Decision Verification 256d Yes/no 10 5 Timing estimation Input: Input: A gate level design, timing info about gates and gate wires Output: Output: Delay estimate – critical path length Delay d=3 d=3 d=4 d=1 d=1 Timing est. d=2 d=2 256d 11 Convergence problems between synthesis and layout Gate network designed without real Knowledge of wire delays d=8 Design spec Logic synthesis Row-based layout d=14 Failure After layout timing violated due to wires 256d 12 6 Incompletely specified functions For incompletely specified function ff we build 3 completely specified functions: ff on , ff dc , ff off . on off dc f on r off on off d off off on ff ffon ff off ff dc f ∪d ∪r On-set the same as On-set of ff On-set the same as Off-set of ff On-set the same as DC-set of ff is a tautology 256d 13 Motivation Commercial success - used almost everywhere VLSI is done Commercial More general treatment of discrete functions of discrete value More variables. Body of useful and general techniques - can be applied to other Body areas. Foundation for: Foundation combinational and sequential synthesis combinational testing testing timing and false paths timing formal verification formal optimal clocking schemes optimal power estimation power general combinatorics. general 256d 14 7 Outline of the class Introduction Introduction Delay in multi-level circuits Delay multi- 2-level combinational circuits Testability of multi-level Testability multi- Binary decision diagrams Binary circuits Synthesis of multi-level Synthesis multi- Boolean matching Boolean circuits Automatic test pattern Automatic Technology mapping Technology generation techniques in logic synthesis 256d 15 Grading Homework assignments : 20% Homework Final project : 70% Final Class presentation of the project : 10% Class You need to do one project for both 256b and 256d. You 256d 16 8 Texts Suggested books: Suggested R.K.Brayton, G.D.Hachtel, C.T.McMullen and R.K.Brayton, G.D.Hachtel, A.Sangiovanni-Vincentelli, “Logic Minimization A.SangiovanniAlgorithms for VLSI Synthesis”, Kluwer Academic Publishers, Boston, MA, 1984. G.D. Hachtel and F.Somenzi, “Logic Synthesis G.D. and Verification Algorithms”, Kluwer Academic Publishers, Boston/Dordrecht/London, 1998. 256d 17 Logic Synthesis Goal: Goal: Map a high level functional description of logic function into a Map set of primitives in a given technology. Automation: Automation: Predominantly for random logic Predominantly Automatic logic synthesis Automatic Functional design (functional specification of the system, Functional transformed into a logic description in terms of Boolean variables) Logic design (manipulation of the logic representation without Logic modification of functionality). 256d 18 9 Physical design Custom (macro-cells) Custom (macrohigh performance, highly optimized designs high Standard cells Standard Gate arrays Gate Field programmable gate arrays Field Do not support highly optimized designs Between macro cells and standard cell: Between algorithmically generated macros produced by module generators. PLA: effective for designing combinational circuits PLA: ROM: look-up table (large Si area) ROM: look256d 19 2-level functions + + . + . OR plane . AND plane inputs PLA are the most popular structures for implementation of 2-level logic PLA 2functions. Input matrix X1 x2 x3 x4 x5 x6 y1 y2 y3 y4 * * 1 1 0 1 0 0 0 0 y1=x3x6’ Output matrix * 1 * * * 1 * * * * * 0 * * * * * * 1 * 0 * 0 * * 0 1 0 1 0 0 0 0 0 0 y2=x2x4’+x1x5 y3=x1’ 0 0 1 0 1 y4=x1x6’+x6 y1 y2 y3 y4 x1 x2 x3 256d x4 x5 x6 20 10 Optimization steps for PLA Logic optimization: reduction of the number of product terms needed to Logic implement the given function. Topological: elimination of unused space; folding and partitioning. Topological Layout and circuit optimization: optimal sizing and placement of drivers, devices Layout and lines. Up to the definitions of the device and interconnect location, PLA is independent Up PLA of implementation technology. Advantages: Advantages: regular structure, easy to automate regular minimization is well understood minimization Disadvantages: Disadvantages: no shape control no little control of speed little little control of I/O placement little 256d PLA (2-level) (2- vs 21 Multi-level Multi- Well developed W ell Technology independent Technology Multi-valued MultiControl logic Control Constrained layout Constrained Automatic layout Automatic Mature Mature Relatively undeveloped Relatively ? ? All (control and data flow) All Flexible, no layout style Flexible, +- Automatic layout Not so Not 256d 22 11 The Boolean n-cube nBn B3 B 4 B0 1 B2 0,1 •B= 2 B •B = 0,1 x 0,1 = 00, 01, 10, 11 256d 23 Basic definitions m n B = { 0,1}, Y = {0,1,2} , a logic function ff.: B -> Y 0,1}, m n x ∈ B is an input, y ∈ Y is an output. 2 - don’t care value ff - incompletely specified function f - a completely specified function ff = (ff1,ff2,,,,ffm) ∀i : 1 ≤ i ≤ m : On-set: X ion ⊆ Bn : such x that ffi(x)=1 OnOff-set: X off ⊆ Bn : such x that ffi(x)=0 Offi Don’t care set: X dc ⊆ Bn : such x that ffi(x)=2 Don such i m=1 : single output function m>1 : multiple output function 256d 24 12 Example Tabular representation Tabular X1 X2 X3 Y1 Y2 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 2 1 1 0 1 1 1 1 1 2 1 on X1 = {[0,0,0],[0,0,1],[1,0,0],[1,0,1], {[0,0,0],[0,0,1],[1,0,0],[1,0,1], [1,1,0]} [1,1,0]} off X1 = {[0,1,0],[0,1,1]} {[0,1,0],[0,1,1]} DC X1 = {[1,1,1]} 256d 25 Boolean functions 0 1 1 f(x) : B n -> B B={0,1}, x={x1,x2,…xn} 1 1 0 n Each vertex of B is mapped to 0 or 1. E ach 0 -1 The onset of f is {x | f(x)=1} = f 1 = f (1) The onset of 0 -1 the offset of f is { x | f(x) =0} = f = f (0) the offset n 1 if f = B , f is the tautology. if t autology If f 0 = B n , f is not satisfiable. If satisfiable. If f(x) = g(x) for all x in B n , then f and g are equivalent. If equivalent. x1, x2, … are variables x1, variables x1, x1’, x2, x2’ … are literals x1, literals 256d 1 26 13 Literals A literal is a variable or its negation : y, y’. literal It represents a logic function logic 1 Literal x1 represents the logic function f, where f = { x | x1 = 1} Literal x1’ represents the logic function g, where g = { x | x1 = 0} 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 0 g = x1’ x1 f = x1 x1 256d 27 Boolean formulas Boolean functions can be represented by formulas defined as Boolean catenations of parentheses - ( , ) parentheses literals - x, y, z, x’, y’, z’. literals Boolean operations - + (or), * (and) Boolean complementations (x+y)’ complementations Examples: Examples: f = x1 * x2’ + x1’ * x2 = (x1+x2) * (x1’ + x2’ ) x1 h= a + b*c = (a’ * (b’ + c’))’ h= We will usually replace * by catenation, e.g. a*b -> ab. We 256d 28 14 Operations on Boolean functions Multiple output functions: the usual Boolean operations are performed component-wise on the outputs. f : B n → B m is a function f : B n → B m such that f 1 , f 2 , , f m have their on-sets equal to the A complement of L off-sets of f. on off off f on f 256d 29 The intersection: h = f ⋅ g ( f ∩ g ) : hi has an on-set equal to the intersection of the on-sets of f i and g i . off f off on off g off on off fg on 256d 30 15 The difference: h = f − g ( f # g) = f ∩ g off f off on off g on off on g on h=f#g on off 256d 31 h = f + g ( f ∪ g) The union: f on off on f The tautology: off set is empty. off on off on off g h 256d 32 16 Incompletely specified functions For incompletely specified function ff we build 3 completely specified functions: ff on , ff dc , ff off . on off dc ffon f on d off on off off off r ff on On-set the same as On-set of ff ff off On-set the same as Off-set of ff ff dc f ∪d ∪r On-set the same as DC-set of ff is a tautology 256d 33 Algebraic representation ffi is an algebraic representation ON of L ff = ( ff1 , ff 2 , X iOFF , and either , ff m ). f i if it is a Boolean expression that evaluates to 1 for all inputs in X i , to 0 for all inputs of DC to 0 or 1 for all inputs in X i . Algebraic representation of ff is denoted by f, f(ff). 256d 34 17 Example x1 x2 x3 y1 y2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 1 0 1 1 0 2 1 1 Can be simplified f1 = x 2 + x1 x 3 f 2 = x2 + x1 x 3 f1 = x1 x 2 x 3 + x1 x 2 x3 + x1 x 2 x 3 + x1 x 2 x3 + x1 x2 x 3 f 2 = x1 x 2 x 3 + x1 x2 x 3 + x1 x2 x3 + x1 x2 x 3 + x1 x2 x3 (Sum of products form) 256d 35 f1 = x 2 + x1 x 3 f 2 = x2 + x1 x 3 Each product term in the sum of products algebraic representation of f determines a logic function. x2 x1 x2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x1 x 3 x3 2-D cube 1 1 0 0 1 1 1 2 x1 0 0 0 0 1 1 1 1 1-D cube 256d x2 x3 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 36 18 Cubes P - a product term in an algebraic sum of products expression of a logic function of n inputs and m outputs ci x x x 0 1 2 3 4 = Example: c = [c1 , c2 , L A cube p is specified by , cn + m ] if appears complemented in p i i=1,2, …,n if appears not complemented in p i if does not appear in p i if p is not present in algebraic representation of i−n if p is present in the algebraic representation of i − n f f i=n+1… n+m f1 = x 2 + x1 x 3 f 2 = x2 + x1 x 3 output cube P= x2 C=[2 0 2 4 3] Input cube 256d 37 Input cube = compact form of the coordinates of the vertices of the cube corresponding to the product term. Example: I(c) = [2 0 represents (1,0,1), (0,0,0), (1,0,0) and (0,0,1). 3] identifies the space where the cube belongs. C = {c1 , c 2 , L O(c) = [4 2] ,ck} is a cover of ff with n inputs and m outputs, if for j=1,2,….m, the set of input parts of the cubes that have a 4 in the j-th position contain all the vertices corresponding to the on-set of and none of the j off-set of , i.e. a cover represents a union of the on-set and some j arbitrary position of the don’t cares. ff ff There is a 1-1 correspondence between a cover and an algebraic representation of a function as a sum-of-products. 256d 38 19 A matrix representation of a cover: L c = [c1 , c2 , M(C) of , cn + m ] is a matrix obtained by stacking the row vectors representing each of the cubes of C. f1 = x 2 + x1 x 3 Example: M(C)= 2 1 2 0 f 2 = x2 + x1 x 3 0 2 1 2 2 0 2 0 4 4 3 3 3 3 4 4 G=I(M(C)) input matrix H=O(M(C)) output matrix Matrix representation and cover are used interchangeably. If C is a cover of a single output function, then H=0 256d be 2 cubes. L c = [c1 , c2 , , cn + m ] and d = [ d1 , d 2 , L Let 39 , d n+m ] The cube c contains d if: the cube represented by the input part of c contains all the vertices of d; and must be present in all Boolean spaces where d is present. A minterm i is a cube whose input part does not contain any 2s and whose output part contains (m-1) 3s and one 4 in position I. e The input cube is a vertex and this vertex is present only in one, I-th Boolean n-space. A minterm does not contain any other cube. If a cube contains a i minterm we say that i is an element of c. e e Example: [1,1,1,4,3] is a minterm and an element of [2,2,1,4,4]. Each cube can be decomposed into a set of all minterms that are elements of the cube. 256d 40 20 Example c=[2, 2, 1, 4, 4] C = [c , c , , c ] covers (c ⊆ C ) if each of the minterms of c e e e e5 e6 e e7 e8 = [1, 0, 1, = [0, 1, 1, = [0, 1, 1, = [1, 1, 1, = [1, 1, 1, 1 2 L A set of cubes 1 = [0, 0, 1, 4, 3] 2 = [0, 0, 1, 3, 4] 3 4 = [1, 0, 1, 4, 3] n+m a cube c is covered by at least one cube of C. Special cubes: 3, 4] 4, 3] 3, 4] 4, 3] 3, 4] uj - the universe of the j-th Boolean space 1,2,……,j….n, n+1, …, n+j, …, n+m 2,………2…2, 3, ….3,…4, ….3….3 U= 1,2,……,j….n, n+1, …, n+j, …, n+m 2,………2…2, 4, ….4,…4, ….4….4 U is the total universe j 1,2,……,j….n, n+1, …, n+j, …, n+m j : the positive half-space of 2,………1…2, 4, ….4,…4, ….4….4 x 256d 41 De Morgan’s law: C = [c , c , 1 2 L x uj = ,c ] n+m 1. Express the cover in algebraic form 2. Exchange AND and OR 3. Change variables to complements Example f = x1 x 3 + x 2 x4 + x1 x2 x 4 f = ( x1 + x3 )( x2 + x 4 )( x1 + x 2 + x4 ) Multiply out using rules of Boolean algebra: . xx = 0 2. xx = x f = x1 x2 + x1 x 4 + x2 x3 x4 + x3 x 4 ( x1 + x 2 ) 3. x + x = 1 256d 42 21 Intersection or a product of 2 cubes c∩d di ci di 1<=i<=n 012 0 1 2 34 ci 000 011 012 0 is an empty cube n<i<=n+m 3 4 33 34 If an output part of a cube has all 3 it is empty. Intersection: input part corresponds to the vertices that are common to c and d. Output part specifies that the cube is present in the Boolean n-spaces in which both c and d are present. If 2 cubes have no common vertices or no common Boolean space: c∩d =0, c and d are orthogonal. f ∩ f =0 256d 43 The union of 2 cubes: c ∪ d (c+d): the set of vertices covered by the input part of either c or d in the Boolean n-space where they are present. In matrix representation: c ∪ d is the matrix formed by 2 rows corresponding to c and d, respectively. The distance between 2 cubes: (# of conflicts) δ (c, d ) = δ ( I (c ), I (d )) + δ (O (c), O (d )) where δ ( I (c), I (d )) =| { j | c j ∩ d j = 0} | δ (O (c ), O ( d )) = 0 if c j ∩ d j = 4 1 otherwise 256d Some j>n 44 22 e = cΘd c ∩ d if δ (c, d ) = 0 δ (c, d ) ≠ 1 then e = 0 if δ (c, d ) ≥ 2 The consensus of 2 cubes: If If δ ( I (c), I (d )) = 1 ∧ δ (O(c ), O( d )) = 0 el = then cl ∩ d l if cl ∩ d l ≠ 0 2 otherwise If δ ( I (c), I (d )) = 0 ∧ δ (O(c ), O(d )) = 1 cl ∩ dl 1 ≤ l ≤ n el = 4 if cl or dl = 4 for n < l ≤ n + m 3 otherwise 256d 45 Theorem: The consensus of 2 cubes a and b, p = aΘb is contained in a ∪ b . If aΘb ≠ 0 , it contains minterms of both a and b. p is the largest cube contained in a ∪b . ∃x, ∃y, x, y ∈ p, x ∈ a, y ∈ b. 256d 46 23 Example 10 8 4 2 6 3 1 9 5 7 cubes consensus c7 = c2 Θc5 c8 = c2Θc6 c9 = c1Θc3 c10 = c5Θc4 c2 Θc3 = 0 c1Θc2 = 0 c3Θc6 = 0 c5Θc6 = 0 256d 47 The complement of a set of cubes C, C covers the complement of logic corresponding to C. The difference: C-H covers C ∩ H . A cube is an implicant of ff=(f,d,r) if it has an empty intersection with the cubes of a representation of r. Example. F=M(C)= 2 1 2 0 0 2 1 2 2 0 2 0 4 4 3 3 3 3 4 4 (1,2,0,4,3) is an implicant of ff. (0,2,1,3,4) is not since it contains (0,0,1) in the Boolean space representing ff2 that is in the off-set of ff2. 256d 48 24 ...
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This note was uploaded on 12/29/2011 for the course ECE 256b taught by Professor Brewer during the Fall '09 term at UCSB.

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