digital_gate_assignment

digital_gate_assignment - ECE194JC/594J PS4 Above is a...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
1 cbi C bb R be C ' ' e b m V g be R ex R + - ' ' e b V cbx C This is the hand analysis model; please use the HBT_scalable model in ADS for circuit simulations. ECE194JC/594J PS4 f m depl be be g C C τ + = , Above is a device model . Recall that . Let us take Cje=5.67 fF, beta=50, Ccbi=1.86 fF, Ccbx=1.34 fF, Rbb=14.7 Ohms, Rex=8 Ohms, and tau_f=0.244 ps. Lets use this device model in circuit calculations below. nKT qI g m / = , where n=1.0. This is the model of a transistor having Ae=0.25 um x 4.0 um emitter area and biased at 1 mA/micron current density (4 mA total); the ft is 470 GHz ft and the fmax 825 GHz. It operates at a maximum of 2.5 mA/um at Vce=1.0 volts. Unlike previous problem sets, do not move all the collector-base capacitance inside Rbb. R L R L R ef R ee -V ee R ef B A C B A C Problem 1: Please find the A-level propagation delay of a CML XOR gate. The circuit diagram is the lower figure: the pull up resistors are 50 Ohm, while the resistors are to act as current sources
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 12/29/2011 for the course ECE 594A taught by Professor Rodwell during the Fall '09 term at UCSB.

Page1 / 4

digital_gate_assignment - ECE194JC/594J PS4 Above is a...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online