mixed_signal_notes_set_2

mixed_signal_notes_set_2 - ECE194J /594J notes, M. Rodwell,...

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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Mixed-Signal IC Design Notes set 2: Fundamentals of Analog IC Design Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Transistor Circuit Design This note set -reviews the basics -starts at the level of a first IC design course -moves very quickly This will -establish a common terminology -accommodate capable students having minimal background in ICs.
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DC models DC bias analysis
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Large-Signal Model For Bias Analysis I c V be I b bandwidth. istor peak trans for required near that densities current at operating HBTs for t significan is drop The resistance emitter the to internal specified is that note ... / where , / and ) / exp( , 0 that Provided ex e ex be T c b T be s c ce R I R V q kT V I I V V I I V = = = > β + -
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 DC Bias Example: Current Mirror 2 / find which we from , 2 and , 2 / implies This area). emitter the is ( that assume & 2 , 1 that Assume ) / ln( , ) / ln( and ) ( ) ( have We 1 2 2 1 2 1 2 1 1 2 2 2 2 1 1 1 2 2 2 2 1 1 1 1 c c s s ex ex E E E ee ee s c t be s c t be ee ex e be ee ex e be I I I I R R A A A R R I I V V I I V V R R I V R R I V = = = = = >> = = + + = + + β 2 ex R 2 ee R 1 ex R 1 ee R 1 e I 1 Q 2 Q 2 e I 2 b I 1 b I 2 c I ref I
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Simpler DC Model for Bias Analysis = = = HBTs GaAs/GaInP V .4 1 HBTs InGaAs/InP V 9 . 0 or 7 . 0 HBTs Si/SiGe Modern V 9 . 0 ~ bias, bandwidth peak of 10% ~ within densities current at Biased y. technolog and density current upon depends . take instead and with of variation the ignore to analysis bias in sufficient often is It , , , φ on be on be on be be c be V V V V I V I c V be I b I c V be I b
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Simple DC Bias Example ee ee c c ee ee c c c e e b b b b R V V I I R V V I I I V V V V R I 2 / ) 9 . 0 ( / ) 9 . 0 ( 2 (SiGe). V 9 . 0 e Approximat Volts. 0 then drops, e neglect th we If 2 1 1 2 1 2 1 2 1 = = = = + = = = = φ I b2 I b1 R ee Q 2 Q 1 -V ee R b R c
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Efficiently Handling Base Currents In Bias Analysis . upon dependent y only weakl bias DC has circuit designed - any well because Works 2 / ) ( solve to of value this use 3) / solve 2) 2 / ) ( solve 1) : iteration by find : Quicker , / where / ) ( 2 : equations us simultaneo solve can one t, singifican is drop If 1 1 1 1 1 1 1 1 1 2 1 β φ ee b b ee c b c b ee ee c c b ee b b ee c c c b b R R I V I I I I R V I I I R R I V I I I R I = = = = = + I b2 I b1 R ee Q 2 Q 1 -V ee R b R c
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Typical Circuit Biasing in Mixed-Signal ICs Biasing with current mirrors more precise--- often more compact but loads emitter node with C cb ---or worse and provides path for stage-stage coupling Resistive biasing--- resistively loads emitter node---lower DC precision I ref I ref
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ECE194J /594J notes, M. Rodwell, copyrighted 2011 Problems with Current Mirror Biasing stage-stage coupling through C cb and the shared current mirror reference. ..
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mixed_signal_notes_set_2 - ECE194J /594J notes, M. Rodwell,...

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