set-cputogpu

set-cputogpu - utogpu-1 cputogpu 3D Rendering Code on...

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Unformatted text preview: utogpu-1 cputogpu- 3D Rendering Code on CPUs & Possible GPU Designs Goal: Find something better than CPU for 3D rendering pipeline code. Plan: By hand analysis find potential performance of rp (rendering pipeline) code. Determine how closely CPU achieves potential. Consider minor CPU modifications. Consider new GPU design. utogpu-1 EE 7700-1 Lecture Transparency. Formatted 11:21, 11 February 2009 from set-cputogpu. cputogpu- utogpu-2 cputogpu- Rendering Pipeline Software CPU Execution Analysis Analysis Performed Using CPU-only “Demo” routines from course. Compiled for SPARCV9 with visual and multiply/add insn. Use Sun Studio 12 compiler with aggressive optimizations. Simulated execution on Fujitsu SPARC64 VI. Use RSIML for simulation and PSE for visualization. utogpu-2 EE 7700-1 Lecture Transparency. Formatted 11:21, 11 February 2009 from set-cputogpu. cputogpu- utogpu-3 cputogpu- Rendering Pipeline Software CPU Execution Analysis SPARCV9 RISC ISA, developed by Sun Microsystems. Has 32 64-bit floating point registers. SPARC64 VI Four-way superscalar. (Can execute up to 4 insn / cycle.) Dynamically scheduled. (Can execute insn out of prog. order.) Can start two FP operations per cycle....
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This note was uploaded on 01/03/2012 for the course EE 7700 taught by Professor Staff during the Spring '08 term at LSU.

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set-cputogpu - utogpu-1 cputogpu 3D Rendering Code on...

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