set-cputogpu

set-cputogpu - utogpu-1 cputogpu- 3D Rendering Code on CPUs...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: utogpu-1 cputogpu- 3D Rendering Code on CPUs & Possible GPU Designs Goal: Find something better than CPU for 3D rendering pipeline code. Plan: By hand analysis find potential performance of rp (rendering pipeline) code. Determine how closely CPU achieves potential. Consider minor CPU modifications. Consider new GPU design. utogpu-1 EE 7700-1 Lecture Transparency. Formatted 11:21, 11 February 2009 from set-cputogpu. cputogpu- utogpu-2 cputogpu- Rendering Pipeline Software CPU Execution Analysis Analysis Performed Using CPU-only Demo routines from course. Compiled for SPARCV9 with visual and multiply/add insn. Use Sun Studio 12 compiler with aggressive optimizations. Simulated execution on Fujitsu SPARC64 VI. Use RSIML for simulation and PSE for visualization. utogpu-2 EE 7700-1 Lecture Transparency. Formatted 11:21, 11 February 2009 from set-cputogpu. cputogpu- utogpu-3 cputogpu- Rendering Pipeline Software CPU Execution Analysis SPARCV9 RISC ISA, developed by Sun Microsystems. Has 32 64-bit floating point registers. SPARC64 VI Four-way superscalar. (Can execute up to 4 insn / cycle.) Dynamically scheduled. (Can execute insn out of prog. order.) Can start two FP operations per cycle....
View Full Document

Page1 / 12

set-cputogpu - utogpu-1 cputogpu- 3D Rendering Code on CPUs...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online