hw05_sol

hw05_sol - LSU EE 2720-2 Homework 5 Solution Due: 28...

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LSU EE 2720-2 Homework 5 Solution Due: 28 November 2011 Please read textbook sections 2.9 and 2.10 (Verilog introduction) in time for Monday’s class. Problem 1: In the 8-input multiplexer below, constructed from smaller multiplexers, the select inputs, s 0 , s 1 , and s 2 , were connected in what would normally be considered the wrong order. That is, if the mux inputs were numbered consecutively starting from the top from 0 to 7 then a select input of 2 would not route the third input to the output. Number the inputs based on the select bits as connected so that if the select bits represent i then input i (using your numbering) is routed to the output. ( Do not change the select bit ordering, even though they are wrong.) Hint: Set the select bits to 3 ( s 2 = 0 , s 1 = 1 , s 0 = 1 ), then Fgure out which input is routed to the output. Label that input 3. Repeat for the other 7 possible select inputs. s
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This note was uploaded on 01/03/2012 for the course EE 2720 taught by Professor Desouza during the Fall '08 term at LSU.

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hw05_sol - LSU EE 2720-2 Homework 5 Solution Due: 28...

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