hw06

# hw06 - LSU EE 2720-2 Problem 1 Homework 6 Due Will not be...

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LSU EE 2720-2 Homework 6 Due: Will not be graded. Problem 1: Consider the pair of logic functions (yes, they are from Homework 5). f 0 = ( a + bc + bcd ) e f 1 = ( a + bc + b cd ) e ( a ) Write a Verilog structural description of a single module implementing these functions. Take advantage of the common terms in the two functions ( a + bc ). ( b ) Notice that one function contains a bcd term and the other contains a b cd term. Though the variables are diFerent the two terms represent the same operation (a three-input AND with one input to the AND inverted). Write a Verilog structural description for these functions taking advantage of this fact by having two modules. One module will be the three-input AND gate just mentioned. The other will compute the functions using two instances of the AND gate. Problem 2: Answer the following questions about EDA (CAD). ( a ) How does a synthesis program know the capabilities of the chip it is targeting, such as the number of gates it can hold? ( b

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## This note was uploaded on 01/03/2012 for the course EE 2720 taught by Professor Desouza during the Fall '08 term at LSU.

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hw06 - LSU EE 2720-2 Problem 1 Homework 6 Due Will not be...

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