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Unformatted text preview: LSU EE 2720-2 Homework 6 Solution Due: Will not be graded. Problem 1: Consider the pair of logic functions (yes, they are from Homework 5). f = ( a + bc + bcd ) e f 1 = ( a + bc + b cd ) e ( a ) Write a Verilog structural description of a single module implementing these functions. Take advantage of the common terms in the two functions ( a + bc ). The solution appears below. Notice that the bc term is shared by the two outputs (the same signal is used for generate sop0 and sop1 ). The ne value is also shared. It would also have been possible to compute a + bc and share that result too. // SOLUTION: module hw6p1a(f1,f0,a,b,c,d,e); input a, b, c, d, e; output f1, f0; wire nb, nc, ne, bc, nbcd, bncd, sop0, sop1; not n1(nb,b); not n2(nc,c); not n3(ne,e); and a1(bc,b,c); and a2(nbcd,nb,c,d); and a3(bncd,b,nc,d); or o1(sop0,a,bc,nbcd); or o2(sop1,a,bc,bncd); and a4(f0,sop0,ne); and a5(f1,sop1,ne); endmodule ( b ) Notice that one function contains a bcd term and the other contains a b cd term. Though the variables are different the two terms represent the same operation (a three-input AND with one input to the AND inverted). Write a Verilog structural description for these functions taking advantage of this fact by having two modules. One module will be the three-input AND gate just mentioned. The other will compute the functions using two instances of the AND gate. Solution appears below. That 3-input and gate is called minterm011 (because the first input is inverted). Notice that it is instantiated twice in module hw6p1b and that the input order is different in the two instances. Use of this minterm011 module avoids the need for two inverters in hw6p1b . The benefit is that hw6p1b is easier for humans to read (assuming they can quickly grasp what minterm011 does). There is no difference in the circuit being described, so simulation and synthesis of the code in this problem and the previous one should be identical. 1 module minterm011(f,i2,i1,i0) input i2, i1, i0; output f; wire ni2; not n1(ni2,i2); and a1(f,ni2,i1,i0); endmodule module hw6p1b(f1,f0,a,b,c,d,e); input a, b, c, d, e; output f1, f0; wire ne, bc, nbcd, bncd, sop0, sop1; not n3(ne,e); and a1(bc,b,c); minterm011 m1(nbcd,b,c,d); minterm011 m2(bncd,c,b,d); or o1(sop0,a,bc,nbcd); or o2(sop1,a,bc,bncd); and a4(f0,sop0,ne); and a5(f1,sop1,ne); endmodule Problem 2: Answer the following questions about EDA (CAD)....
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This note was uploaded on 01/03/2012 for the course EE 2720 taught by Professor Desouza during the Fall '08 term at LSU.
- Fall '08