high_voltage_vm_driver_fukuda_isscc_2008

high_voltage_vm_driver_fukuda_isscc_2008 - 98 2008 IEEE...

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Unformatted text preview: 98 2008 IEEE International Solid-State Circuits Conference ISSCC 2008 / SESSION 5 / HIGH-SPEED TRANSCEIVERS / 5.1 5.1 An 8Gb/s Transceiver with 3-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane K. Fukuda 1 , H. Yamashita 1 , F. Yuki 1 , M. Yagyu 1 , R. Nemoto 1 , T. Takemoto 1 , T. Saito 1 , N. Chujo 2 , K. Yamamoto 2 , H. Kanai 2 , A. Hayashi 1 1 Hitachi, Tokyo, Japan, 2 Hitachi, Kanagawa, Japan IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/s dB/mW). A block diagram of the half-rate transmitter with a 5-tap FFE is shown in Fig. 5.1.1. A 5b data stream from a shift register is inverted every other bit and fed into output drivers that consist of 25 CMOS inverters in parallel. FFE tap coefficients are determined by the number of inverters that each bit drives. The output impedance is adjusted to 50 by variable resistors consisting of pass transistors. A block diagram of the half-rate receiver is shown in Fig. 5.1.2. The VGA has a gain range of 12dB. The variable analog equalizer using a capacitive feedback amplifier has a maximum 12dB gain peaking at 4GHz compared to that at 0Hz. Two offset amplifiers and 8 latches make up the half-rate 2-tap DFE combined with a 3-oversampling 2-threshold eye-tracking CDR circuit, which is the main component described in this paper. The 2-tap DFE is achieved by the loop-unrolling technique. The input signal is divided into two signals, DH and DL, and fed into 8 latches for data determination and clock recovery. The clock recovery (CR) method is a significant issue for receivers with DFE. Conventional CR circuits operate on a non-DFE equalized signal [1]. However, particularly for loop-unrolling DFE, this approach increases circuit complexity and power because an additional amplifier for the non-DFE signal is needed. To make matters worse, large jitter in a non-DFE equalized signal causes large jitter in the recovered clock. Performing CR on a post-DFE signal is preferable, because its edges exhibit lower jitter. However, a conventional 2- oversampling Alexander phase detector (PD) with data and edge sampling cannot maintain the data sampling at the center of the eye, because the time difference between the edge and the eye center of the post-DFE signal is not equal to 0.5UI. To eliminate this defect, data sampling and edge sampling must operate on...
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This note was uploaded on 01/01/2012 for the course ECEN 689 taught by Professor Enjeti during the Spring '07 term at Texas A&M.

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high_voltage_vm_driver_fukuda_isscc_2008 - 98 2008 IEEE...

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