lecture1_ee689_intro

lecture1_ee689_intro - ECEN689: Special Topics in...

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Sam Palermo ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 1: Introduction
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Class Topics System and design issues relevant to high-speed electrical (and optical) signaling Channel properties Modeling, measurements, communication techniques High-Speed link circuits Drivers, receivers, equalizers, timing systems Link system design Modeling and performance metrics Link system examples 2
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Administrative Instructor: Sam Palermo 315E WERC Bldg., 845-4114, spalermo@ece.tamu.edu Office hours: TR 9:00am-10:30pm Lectures: MWF 10:20am-11:10am, ZACH 333A Class web page http://www.ece.tamu.edu/~spalermo/ecen689.html 3
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Class Material Textbook: Class Notes and Technical Papers Key References Digital Systems Engineering, W. Dally and J. Poulton, Cambridge University Press, 1998. Advanced Signal Integrity for High-Speed Digital Designs, S. H. Hall and H. L. Heck, John Wiley & Sons, 2009. High-Speed Digital Design: A Handbook of Black Magic, H. Design of Integrated Circuits for Optical Communications, B. Razavi, McGraw-Hill, 2003. Class notes Will hand out hard copies in class 4
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Grading Exams (50%) Two midterm exams (25% each) Labs (Prelab + Report) and homeworks weighted equally Collaboration is allowed, but independent simulations and write-ups Need to setup CADENCE simulation environment Due at beginning of class No late homework will be graded Final Project (25%) Groups of 1-2 students Report and PowerPoint presentation required 5
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Prerequisites This is a circuits AND systems class Circuits ECEN474 or approval of instructor Basic knowledge of CMOS gates, flops, etc… Circuit simulation experience (HSPICE, Spectre) Systems Basic knowledge of s- and z-transforms Basic digital communication knowledge MATLAB experience 6
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Simulation Tools Matlab Stateye (Statistical BER link analysis) Cadence 90nm CMOS device models Can use other technology models if they are a 90nm or more advanced CMOS node Other tools, schematic, layout, etc… are optional 7
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Desktop Computer I/O Architecture Many high-speed I/O interfaces Key bandwidth bottleneck points are memory (FSB) and graphics interfaces (PCIe) Near-term architectures ̶ Integrated memory controller with
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This note was uploaded on 01/01/2012 for the course ECEN 689 taught by Professor Enjeti during the Spring '07 term at Texas A&M.

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lecture1_ee689_intro - ECEN689: Special Topics in...

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