lecture9_ee689_txmux

lecture9_ee689_txmux - ECEN689: Special Topics in...

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Sam Palermo ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 9: TX Multiplexer Circuits
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Next Week Shan will give Monday lecture at normal time No class next Wednesday I’ll be back for Friday’s lecture Reading Will post some papers on high-order TX multiplexer circuits TX circuit speed limitations Clock distribution Multiplexing techniques 2
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TX Circuit Speed Limitations High-speed links can be limited by both the channel and the circuits Clock generation and distribution is key circuit bandwidth bottleneck Multiplexing circuitry also limits maximum data rate 3
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TX Multiplexer – Full Rate 4 Tree-mux architecture with cascaded 2:1 stages often used Full-rate architecture relaxes clock duty- cycle, but limits max data rate Need to generate and distribute high-speed clock Need to design high- speed flip-flop
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TX Multiplexer – Full Rate Example 5 [ Cao JSSC 2002 ] CML logic sometimes used in last stages Minimize CML to save power 10Gb/s in 0.18 µ m CMOS 130mW!!
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This note was uploaded on 01/01/2012 for the course ECEN 689 taught by Professor Enjeti during the Spring '07 term at Texas A&M.

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lecture9_ee689_txmux - ECEN689: Special Topics in...

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