lecture13_ee689_rxeq

lecture13_ee689_rxeq - ECEN689: Special Topics in...

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Sam Palermo ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 13: RX FIR, CTLE, & DFE Equalization
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Announcements Exam 1 is March 9 10:20-11:20AM (10 extra minutes) Closed book w/ one standard note sheet Bring your calculator Covers material through lecture 10 Last year’s exam 1 is posted on the website for reference DFE-IIR paper posted on website 2
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Agenda RX FIR Equalization RX CTLE Equalization RX DFE Equalization 3
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Link with Equalization 4 Serializer D TX [N:0] TX Clk Generation (PLL) TX FIR Equalization RX Clk Recovery (CDR/Fwd Clk) Σ RX CTLE + DFE Equalization Deserializer D RX [N:0] Channel f
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TX FIR Equalization 5 TX FIR filter pre-distorts transmitted pulse in order to invert channel distortion at the cost of attenuated transmit signal (de-emphasis) z -1 z -1 z -1 w -1 w 0 w 1 w 2 TX data z -1 w n
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RX FIR Equalization Delay analog input signal and multiply by equalization coefficients Pros With sufficient dynamic range, can amplify high frequency content (rather than attenuate low frequencies) Can cancel ISI in pre-cursor and beyond filter span Filter tap coefficients can be adaptively tuned without any back-channel Cons Amplifies noise/crosstalk Implementation of analog delays Tap precision 6 [ Hall ]
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RX Equalization Noise Enhancement Linear RX equalizers don’t discriminate between signal, noise, and cross-talk While signal-to-distortion (ISI) ratio is improved, SNR remains unchanged 7 [ Hall ]
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Analog RX FIR Equalization Example 8 D. Hernandez-Garduno and J. Silva-Martinez, “A CMOS 1Gb/s 5-Tap Transversal Equalizer based on 3 rd -Order Delay Cells," ISSCC, 2007. 5-tap equalizer with tap spacing of T b /2 1Gb/s experimental results 3 rd -order delay cell
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Digital RX FIR Equalization Digitize the input signal with high-speed low/medium resolution ADC and perform equalization in digital domain Digital delays, multipliers, adders Limited to ADC resolution Power can be high due to very fast ADC 9 [ Hanumolu]
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10 [ Harwood ISSCC 2007 ] 12.5GS/s 4.5-bit Flash ADC in 65nm CMOS XCVR power (inc. TX) = 330mW, Analog = 245mW, Digital = 85mW
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lecture13_ee689_rxeq - ECEN689: Special Topics in...

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