lecture16_ee689_clocking_architectures

lecture16_ee689_clocking_architectures - ECEN689 Special...

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Sam Palermo Analog & Mixed-Signal Center Texas A&M University ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 16: Clocking Architectures
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Announcements & Agenda Lab 5 report and lab 6 prelab due next Friday Clocking Architectures High-speed link clocking tutorial paper posted on website 2
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High-Speed Electrical Link System 3
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Clocking Terminology 4 Synchronous Every chip gets same frequency AND phase Used in low-speed busses Mesochronous Same frequency, but unknown phase Requires phase recovery circuitry Can do with or without full CDR Used in fast memories, internal system interfaces, MAC/Packet interfaces Plesiochronous Almost the same frequency, resulting in slowly drifting phase Requires CDR Widely used in high-speed links Asynchronous No clocks at all Request/acknowledge handshake procedure Used in embeddded systems, Unix, Linux [ Poulton ]
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I/O Clocking Architectures Three basic I/O architectures Common Clock (Synchronous) Forward Clock (Source Synchronous)
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