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lecture17_ee689_plls

lecture17_ee689_plls - ECEN689 Special Topics in High-Speed...

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Sam Palermo Analog & Mixed-Signal Center Texas A&M University ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 17: Phase-Locked Loops
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Announcements Project will be assigned this week Reading Posted PLL analysis paper and thesis on website Posted PLL models in lab section Website additional links has PLL and jitter tutorials Majority of today’s material from Fischette tutorial and M. Mansuri’s PhD thesis (UCLA) 2
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Agenda PLL modeling PLL noise transfer functions PLL circuits PLL design procedure 3
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Introduction A phase-locked loop (PLL) is a negative feedback system where an oscillator-generated signal is phase AND frequency locked to a reference signal PLLs applications Frequency synthesis Multiplying a 100MHz reference clock to 10GHz Skew cancellation Phase aligning an internal clock to an I/O clock Clock recovery Extract from incoming data stream the clock frequency and optimum phase of high-speed sampling clocks Modulation/De-modulation Wireless systems Spread-spectrum clocking 4
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Forward Clock I/O Circuits 5 TX PLL TX Clock Distribution Replica TX Clock Driver Channel Forward Clock Amplifier RX Clock Distribution De-Skew Circuit DLL/PI Injection-Locked Oscillator
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Embedded Clock I/O Circuits 6 TX PLL TX Clock Distribution CDR Per-channel PLL-based Dual-loop w/ Global PLL & Local DLL/PI Local Phase-Rotator PLLs Global PLL requires RX clock distribution to individual channels
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PLL Block Diagram 7 [ Mansuri ]
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Linear PLL Model 8
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Phase Detector Detects phase difference between feedback clock and reference clock The loop filter will filter the phase detector output, thus to characterize phase detector gain, extract average output voltage (or current for charge-pump PLLs) 9 φ ref φ fb φ e
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Loop Filter Lowpass filter extracts average of phase detector error pulses 10 I I VCO Control Voltage C 1 R C 2 Charging Discharging VDD VSS F(s)
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