lecture18_ee689_cdrs

lecture18_ee689_cdrs - Sam Palermo Analog &...

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Unformatted text preview: Sam Palermo Analog & Mixed-Signal Center Texas A&M University ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 18: CDRs Announcements Project preliminary report #1 due on Friday in class Topic description Literature survey Initial architecture(s) Initial simulations 2 Agenda CDR overview CDR phase detectors Analog & digital CDRs Dual-loop CDRs CDR circuits Phase interpolators Delay-locked loops CDR jitter properties 3 Embedded Clock I/O Circuits 4 TX PLL TX Clock Distribution CDR Per-channel PLL-based Dual-loop w/ Global PLL & Local DLL/PI Local Phase-Rotator PLLs Global PLL requires RX clock distribution to individual channels 5 Embedded Clocking (CDR) early/ late RX PD CP V CTRL integral gain proportional gain VCO D in Loop Filter RX [n:0] FSM sel early/ late Phase-Recovery Loop RX PD [4:0] CP V ctrl Frequency Synthesis PLL 5-stage coupled VCO 4 800MHZ Ref Clk PFD PLL [4:0] (16Gb/s) 5 Mux/ Interpolator Pairs 5:1 MUX 5:1 MUX PLL [4:0] (3.2GHz) PLL [0] 15 10 PLL-based CDR Dual-Loop CDR Clock frequency and optimum phase position are extracted from incoming data Phase detection continuously running Jitter tracking limited by CDR bandwidth With technology scaling we can make CDRs with higher bandwidths and the jitter tracking advantages of source synchronous systems is diminished Possible CDR implementations Stand-alone PLL Dual-loop architecture with a PLL or DLL and phase interpolators (PI) Phase-rotator PLL CDR Phase Detectors CDR phase detectors compare the phase between the input data and the recovered clock sampling this data and provides information to adjust the sampling clocks phase Phase detectors can be linear or non-linear Linear phase detectors provide both sign and magnitude information regarding the sampling phase error Hogge Non-linear phase detectors provide only sign information regarding the sampling phase error Alexander or 2x-Oversampled or Bang-Bang Oversampling (>2) Baud-Rate 6 Late Tb/2 ref Hogge Phase Detector Linear phase detector With a data transition and assuming a full-rate clock The late signal produces a signal whose pulse width is proportional to the phase difference between the incoming data and the sampling clock A Tb/2 reference signal is produced with a Tb/2 delay If the clock is sampling early, the late signal will be shorter than Tb/2 and vice-versa 7 Late Tb/2 ref [Razavi] Late Tb/2 ref Hogge Phase Detector For phase transfer 0rad is w.r.t optimal Tb/2 ( ) spacing between sampling clock and data e = in clk TD is the transition density no transitions, no information A value of 0.5 can be assumed for random data 8 Late Tb/2 ref (Late Tb/2 ref) 1 Average Output Amplitude -1 Average Output Amplitude ( ) TD K PD 1 = [Razavi] [Lee] Hogge Phase Detector Nonidealities...
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lecture18_ee689_cdrs - Sam Palermo Analog &...

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