lecture19_ee689_fwd_clk_deskew

lecture19_ee689_fwd_clk_deskew - ECEN689: Special Topics in...

Info iconThis preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon
Sam Palermo Analog & Mixed-Signal Center Texas A&M University ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 19: Forwarded Clock Deskew Circuits
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Announcements No class on Friday Project preliminary report #2 due on Monday in class Expand on report #1 Project feedback meetings during Thursday office hours (9-10:30AM) Exam 2 is on Friday April 29 Comprehensive, but will focus on lectures 11 and later 60 minutes 1 standard 8.5x11 note sheet (front & back) Bring your calculator 2
Background image of page 2
Agenda Forwarded Clock I/O Overview Data & Clock Skew Performance Impact Jitter Impulse Response and Jitter Transfer Function Forwarded Clock Deskew Architectures PLL/PI DLL/PI ILO Fundamental, Super-Harmonic, Sub-Harmonic 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Forwarded Clock I/O Architecture 4 Common high-speed reference clock is forwarded from TX chip to RX chip Mesochronous system Used in processor-memory interfaces and multi-processor communication Intel QPI Hypertransport Requires one extra clock channel “Coherent” clocking allows low- to-high frequency jitter tracking Need good clock receive amplifier as the forwarded clock is attenuated by the channel
Background image of page 4
Forwarded Clock I/O Limitations 5 Clock skew can limited forward clock I/O performance Driver strength and loading mismatches Interconnect length mismatches Low pass channel causes jitter amplification Duty-Cycle variations of forwarded clock
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Forwarded Clock I/O De-Skew 6 Per-channel de-skew allows for significant data rate increases Sample clock adjusted to center clock on the incoming data eye Implementations Delay-Locked Loop and Phase Interpolators Injection-Locked Oscillators Phase Acquisition can be BER based – no additional input phase samplers Phase detector based implemented with additional input phase samplers periodically powered on
Background image of page 6
Forwarded Clock I/O Circuits 7 TX PLL TX Clock Distribution Replica TX Clock Driver Channel Forward Clock Amplifier RX Clock Distribution De-Skew Circuit PLL/PI DLL/PI Injection-Locked Oscillator
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Data & Clock Skew Performance Impact 8 High speed forwarded clock allows jitter tracking between clock and data Clock to data skew causes that high frequency clock and data jitters become out of phase on the receiver
Background image of page 8
Impact of Clock to Data Skew on Jitter Tracking 9 UI = 100ps Assuming 5UI skew in this example Jitter Frequency = 100MHz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10 -8 -0.5 0 0.5 data jitter JD(UI) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10 -8 -0.5 0 0.5 clock jitter JC(UI) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10 -8 -0.5 0 0.5 differential jitter Jdiff(UI) time skew of mUI between data and clock
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Impact of Clock to Data Skew on Jitter Tracking 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10 -8 -0.5 0 0.5 data jitter JD(UI) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10 -8 -0.5 0 0.5 clock jitter JC(UI) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 x 10 -8 -0.5 0 0.5 differential jitter Jdiff(UI) time Jitter Frequency = 200MHz
Background image of page 10
Impact of Clock to Data Skew on Jitter Tracking 11
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 12
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 50

lecture19_ee689_fwd_clk_deskew - ECEN689: Special Topics in...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online