lecture20_ee689_clk_distribution

lecture20_ee689_clk_distribution - ECEN689: Special Topics...

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Sam Palermo ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 20: Clock Distribution Techniques
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Announcements Project preliminary report #2 due now Exam 2 is on Friday April 29 Comprehensive, but will focus on lectures 11 and later 60 minutes Bring your calculator Lab solutions and last years exam posted on website 2
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Agenda Clock distribution in serial I/O systems Wire scaling Clock distribution techniques Inverter Chain CML Chain Transmission Line Inductive Load Capacitively Driven Wires CML2CMOS converters 3
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Clock Distribution in Serial I/O Systems 4 On-die global clock distribution is necessary in multi-channel embedded and fowarded clock serial link systems Forwarded Clock System Embedded Clock System
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VLSI Interconnect (Wires) 5 [Bohr ISSCC 2009] 45nm CMOS
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Wire Scaling Ideally, we scale everything by 0.7x when we move to a more advanced technology node for 2x density Results in 2x wire resistance, which dramatically increases wire RC delay To compensate resistance wires get taller Cap grows at a smaller pace with scaling Taller wires increase sidewall cap Improved (low-k) dielectrics help reduce cap 6 Node “N” Node “N+1” (ideal scaling) Node “N+1” (actual scaling) [Ho]
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Wire Scaling - Delay Global on-chip wire RC delay becomes many (100+) gate delays (if driven w/ one lumped driver) 7 [Ho Proc. IEEE 2001] FO4 delay 1cm wire
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Limited Wire Bandwidth Global on-chip wire bandwidth is much worse than chip- to-chip channels RC-dominated on- chip wires vs (R)LC-dominated off-chip wires 8
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Clock distribution techniques are typically compared in regards to jitter, delay, and power
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lecture20_ee689_clk_distribution - ECEN689: Special Topics...

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