Ae104a10_solutions_5

# Ae104a10_solutions_5 - Ae/APh 104a Homework Solution Set#5...

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Unformatted text preview: Ae/APh 104a Homework Solution Set #5 1/4 Recall the ideal op-amp assumptions: v + = v- in all cases and no current across the input terminals. (a) Integrator v- = v + = 0 , i R = v in- R F = i C . So- i C = C 1 dv out dt and v out =- 1 R F C 1 Z v in dt for v out = 0 at t = 0. (b) High impedance (first two op-amps are buffers) and common mode rejection Consider the output op-amp first, and KCL at input and output in terms of the voltage at output from the lefthand top and bottom op-amps: v out- v- R 2 = v-- v out,top cR 2 ,- v + R 2 = v +- v out,bottom cR 2 . Then, subtracting v out = v out,bottom- v out,top c . Working on the lefthand op-amps: v out,top- v out,bottom = iR 1 (1 + a + b ) and i = v 1- v 2 R 1 . 1 Substituting, v out = 1 + a + b c ( v 2- v 1 ) . (c) Exponential output As in part (a), but with given current law for diode, i d = e v in = i R ,- v out = i R R and v out =- Re v in . 2/4 (a) (i) KVL on lefthand loop with R L , such that V out = V oc :- v test + i test R i + R o i test + A ( v +- v- ) = 0 v- = v oc , v + = v test i test = v +- v- R i = v test- v oc R i so, substituting,- v oc + R o R i ( V test- V oc ) + A ( v test- v oc ) = 0 and A v oc v test = R o + AR i R o + ( A + 1) R i . (ii) As before from loop 1 (lefthand loop) v + = v test i test = i 1 i test = v +- v- R i = v test- v- R i and- v test + i test R i + R o ( i test- i 2 ) + A ( v +- v- ) = 0 . From loop 2 (righthand loop)- A ( v +- v- ) + ( i 2- i test ) R o + i 2 R L = 0 , 2 so we have- AR i i test + ( i 2- i test ) R o + R l i 2 = 0 and AR i i test- ( i 2- i test ) R o + R l i test = v test ....
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Ae104a10_solutions_5 - Ae/APh 104a Homework Solution Set#5...

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