1intro - VHDL Main topics s Circuit design based on VHDL s...

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Unformatted text preview: VHDL Main topics: s Circuit design based on VHDL s VHDL basics s Advanced VHDL language structures s Circuit examples Introduction to VHDL Shortly About the VHDL s s s s VHDL is an acronym of VHSIC Hardware Description Language Language VHSIC is an acronym of Very High Speed Integrated Circuits Circuits A Formal Language for Specifying the Behavior and Formal Structure of a Digital Circuit Structure Allows Top-Down Design Introduction to VHDL Gajski’s Y-chart Gajski’s Behavior Structural Sequential programs Processors, memories Registers, FUs, MUXs Each axis represents type of description – Behavioral Defines outputs as function of inputs Algorithms but no implementation – Structural Implements behavior by connecting components with known behavior – Physical Gives size/locations of components and wires on chip/board – Design process is illustrated by travel route Register transfers Gates, flip-flops Logic equations/FSM Transistors Transfer functions Cell Layout Modules Chips Boards Physical VHDL for Simulation & Synthesis VHDL Test Vector Generator Test Vectors Executable Specification = A Series of Refined Models Final Chip Model Results, Errors VHDL for Simulation & Synthesis VHDL VHDL requirements for Simulation VHDL s Creation of test benches => – – – – File I/O Detection of errors (function & timing) Multiple simultaneous models Combination of low & high level models (for efficiency) VHDL for Simulation & Synthesis VHDL VHDL requirements for HW Description VHDL s Behavioral models => Behavioral – Combinatorial & Sequential Logic – RTL models s s Structural models Timing models Timing VHDL for Simulation & Synthesis VHDL Requirements for VHDL Synthesis Tools s Pre- & post synthesis behavior should be identical s Synthesis should be efficient => – – – – Requires interaction with place & route tools Logic Synthesis FSM Synthesis Area & Timing Optimization New possibilities New s VHDL frees the designer from having to use von VHDL Neumann structures Neumann – (Neumann János = John von Neumann) s s It allows him to work with real concurrency instead of It sequential machines sequential This opens up completely new possibilities for the This designer designer Reasons for using VHDL Reasons s s s Shorter development times for electronic design Simpler maintenance Traditional way: schematic design Origin of the VHDL s VHDL originated in the early 1980s – The American Department of Defense initiated the development he of VHDL in the early 1980s of » because the US military needed a standardized method of describing because electronic systems electronic s s VHDL was standardized in 1987 by the IEEE It is now accepted as one of the most important standard It languages for languages – specifying – verifying verifying – designing of electronics Introduction to VHDL Standardization 1 Standardization s s IEEE standard specification language (IEEE 1076-1993) IEEE for describing digital hardware used by industry worldwide worldwide VHDL enables hardware modeling from the gate level to VHDL the system level the All the major tool manufacturers now support the VHDL All standard standard s VHDL is now a standardized language, with the advantage VHDL that it is easy to move VHDL code between different that commercial platforms (tools) commercial => VHDL code is interchangeable among the different tools s Standardization 2 VHDL is an acronym of VHSIC Hardware Description VHDL Language Language s VHSIC is an acronym of Very High Speed Integrated VHSIC Circuits Circuits s All the major tool manufacturers now support the VHDL All standard standard s VHDL is now a standardized language, with the advantage VHDL that it it easy to move VHDL code between different commercial platforms (tools) commercial => VHDL code is interchangeable among the different tools s Introduction to VHDL Standardization 3 s s It was the American Department of Defense which initiated It the development of VHDL in the early 1980s because the US military needed a standardized method of describing electronic systems electronic VHDL was standardized in 1987 by the IEEE – IEEE Std-1076-1987 s s ANSI Standard in 1988 Added Support for RTL Design – VITAL: VHDL Initiative Towards ASIC Library s Revised version in 1993 – IEEE Std-1076-1993 Introduction to VHDL Standardization 4 s 1995: 1995: – numeric_std/bit: IEEE-1076.3 – VITAL: IEEE-1076.4 s s 1999: IEEE-1076.1 (VHDL-AMS ) 2000: 2000: – IEEE-1076-2000 – IEEE-1076.1-2000 (VITAL-2000, SDF 4.0) s Added mixed-signal support to VHDL in 2001 -> – VHDL-AMS » IEEE Std-1076.1-2001 s 2002: IEEE-1076-2002 Introduction to VHDL Tools Tools s s s Good VHDL tools, and VHDL simulators in particular, Good have also been developed for PCs have Prices have fallen dramatically, enabling smaller Prices companies to use VHDL, too companies There are also PC synthesis tools, primarily for FPGAs There and EPLDs and Usage Usage s High-tech companies – Texas Instruments, Intel use VHDL – most European companies use VHDL s s Universities VHDL groups to support new users IEEE IEEE s s s s IEEE is the Institute of Electrical and Electronics IEEE Engineers Engineers The reference manual is called IEEE VHDL Language The Reference Manual Draft Standard version 1076/B Reference It was ratified in December 1987 as IEEE 1076-1987 Important: – the VHDL is standardized for system specification the system – but not for design Technology independence Technology s s s The design of VHDL components can be technologyindependent or more-or-less technology independent for a independent technical family technical The components can be stored in a library for reuse in several The different designs different VHDL models of commercial IC standard components can now VHDL be bought, which is a great advantage when it comes to verifying entire circuit boards entire Analog world Analog s s s VHDL has not yet been standardized for analog VHDL electronics electronics Standardization is in progress on VHDL with an analog Standardization extension (AHDL) to allow analog systems to be described as well as This new standard will be based wholly on the VHDL This standard and will have a number of additions for describing analog functions describing VHDL-Related Newsgroups comp.arch.fpga s comp.lang.vhdl s comp.cad.synthesis s Introduction to VHDL Other HDL languages s There are several other language extensions built to either aid in RTL construction There or assist in modeling: or – – – – – – – – ParaCore - http://www.dilloneng.com/paracore.shtml ParaCore http://www.dilloneng.com/paracore.shtml RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml RubyHDL http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml MyHDL http://jandecaluwe.com/Tools/MyHDL/Overview.shtml JHDL - http://www.jhdl.org/ JHDL http://www.jhdl.org/ Lava - http://www.xilinx.com/labs/lava/ Lava http://www.xilinx.com/labs/lava/ HDLmaker - http://www.polybus.com/hdlmaker/users_guide/ HDLmaker http://www.polybus.com/hdlmaker/users_guide/ SystemC SystemC AHDL – http://www.altera.com http://www.altera.com » It is good for Altera-made chips only, which limits its usefulness It is for » But it is easy to pick up and use successfully use s The main purpose of a language -- programming, hdl, or otherwise -- is to ease the The expression of design expression Introduction to VHDL Verilog s s Verifying Logic Phil Moorby from Gateway Design Automation in 1984 to 1987 – Absorbed by Cadence » Cadence's ownership of Verilog => others support VHDL s s s Verilog-XL simulator from GDA in 1986 Synopsis Synthesis Tool in 1988 In 1990 became open language – OVI: Open Verilog International s IEEE Standard in 1995 – IEEE Std-1364-1995 s Last revision in 2001 – IEEE Std-1364-2001 s Ongoing work for adding – Mixed-signal constructs: Verilog-AMS – System-level constructs: SystemVerilog Introduction to VHDL VHDL vs. Verilog VHDL Verilog All abstraction levels All abstraction levels Complex grammar Easy language Describe a system (everything) Describe a digital system Lots of data types Few data types User-defined package & library No user-defined packages Full design parameterization Simple parameterization Easier to handle large designs Very consistent language. Code written and ery simulated in one simulator will behave exactly the same in another simulator. E.g. exactly strong typing rules. strong Less consistent language. If you don't ess follow some adhoc methodology for coding styles, you will not get it right. styles, It executes differently on different platforms unless you follow some adhoc coding rules. unless you Introduction to VHDL VHDL vs. Verilog (Cont.) s s It does seem that Verilog is easier for designing at the It Verilog gate-level, but that people who do higher level simulations express a preference for VHDL VHDL VHDL places constraints on evaluation order that limit the optimizations that can be performed – Verilog allows the simulator greater freedom greater – For example, multiple levels of zero-delay gates can be collapsed into a single super-gate evaluation in Verilog super-gate – VHDL requires preserving the original number of delta cycles of delay in propagating through those levels VHDL Verilog In Europe the VHDL is the most popular In language language Based on Pascal language Based on C language Most FPGA design in VHDL Most ASIC design in Verilog Most ASIC Introduction to VHDL VHDL vs. Verilog: Process block s VHDL: process (siga, sigb) begin …... end; s Verilog: always @ (siga or sigb) begin …. end Introduction to VHDL VHDL vs. Verilog: Concurrent Signal Assignment s VHDL: c <= a and b; s Verilog: assign c = a & b ; Introduction to VHDL VHDL vs. Verilog: Signal Delays s VHDL: a <= transport b after 1 ns; s Verilog: » » » » » #1 assign a = b; ‘a’ output is delayed by 1 time unit The ‘# ‘ operator is the delay operator # N will delay for N simulation units Delays can assigned to both inputs and outputs #1 assign a = #1 b; ‘b’ is delayed by 1 unit, then assigned to ‘a’, which is then delayed by 1 time unit Introduction to VHDL VHDL vs. Verilog: Clock Generator s VHDL: signal clk : std_logic := ‘0’; process begin clk <= not (clk) after clkperiod/2; wait on clk; end; s Verilog: initial clk = 0; always #(clkperiod/2) clk = ~ clk; Introduction to VHDL Verilog Weakness s Not well suited for complex, high level modeling – – – – No user defined type definition No concept of libraries, packages, configurations No ‘generate’ statement - can’t build parameterized structural models No complex types above a two-dimensional array Introduction to VHDL VHDL vs. Verilog: Managing Large designs s VHDL: – Configuration, generate, generic and package statements all help manage Configuration, large design structures large s Verilog: – There are no statements in Verilog that help manage large designs Introduction to VHDL VHDL vs. Verilog: Procedures and Tasks s VHDL: – allows concurrent procedure calls s Verilog: – does not allow concurrent task calls Introduction to VHDL VHDL vs. Verilog: Structural Replication s VHDL: – The generate statement replicates a number of instances The of the same design-unit or some sub part of a design, and connects it appropriately s Verilog: – There is no equivalent to the generate statement in There Verilog. Verilog. Introduction to VHDL Languages “under development” s SystemVerilog – Extending Verilog to higher levels of abstraction for architectural and Extending algorithm design and advanced verification algorithm s VHDL 200x – Goal of VHDL Analysis and Standards Group (VASG): » Enhance/update VHDL for to improve performance, modeling capability, Enhance/update ease of use, simulation control, and the type system ease s e.g.: Data types and abstractions: e.g.: Data – variant records – interfaces Introduction to VHDL ...
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