Altera - Copyright © 2003 Altera Corporation Copyright ©...

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Unformatted text preview: Copyright © 2003 Altera Corporation Copyright © 2003 Altera Corporation Robert Blake Vice President, Product Planning History of Programmable Logic Copyright © 2003 Altera Corporation Copyright © 2003 Altera Corporation Altera Founded in 1983 “ The probabilities are high that someone will produce an electrically alterable logic array ” predicted Bob Hartmann, Paul Newhagen and Michael Magranet in the closing chapters of their 1982 book on the gate array industry They recognized limitations of ASICs and the value of PROGRAMABILITY World’s First PLD EP300: 320 Gates, 3-µm CMOS- 10-MHz Performance, 20 I/O Pins- Desktop Programming- “Fixing Design Errors for Free” First Fabless Company History of PLDs - 1984 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 CMOS PLD $B 0.5 1.0 1.5 2.0 2.5 3.0 First PLD History of PLDs: 1985 - 1987 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 TTL Libraries (74XX) for PLD EP1200 First High-Density PLD EPB1400 First Embedded PLD First PLD TTL LIB EP1200 EPB1400 CMOS PLD $B 0.5 1.0 1.5 2.0 2.5 3.0 Simple Control Logic History of PLDs: 1988 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD Altera IPO March 30, 1988 ALTR Offers 4 Million Shares MAX+PLUS ® Software: First Integrated EDA for PLDs ALTR IPO TTL LIB EP1200 EPB1400 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B Simple Control Logic History of PLDs: 1989 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD Altera Delivers Hardware Description Language (AHDL) >50% Reduction in Design Entry Time >5,000 Customers TTL LIB EP1200 EPB1400 ALTR IPO AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B Complex Logic Simple Control Logic History of PLDs: 1990-1991 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 MAX+PLUS II MAX 7000 ALTR IPO Introduction of MAX ® 7000 – Now World’s Most Popular PLD Ever! MAX+PLUS ® II: First Windows-Based Integrated Tools AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B Complex Logic Simple Control Logic History of PLDs: 1992 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 FLEX 8000 ACCESS EDA ALTR IPO MAX+PLUS II MAX 7000 AHDL FLEX ® 8000 High-Density/Performance SRAM FPGA- >1M Transistors- Bridging & System Logic Integration ACCESS SM Program- Industry Alliance with EDA Manufacturers Adopted ASIC Design Methodology 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B Complex Logic System Logic Simple Control Logic History of PLDs: 1993-1994 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD World’s First Low-Power 3.3-V CPLD MAX 9000 High-Density CPLD- 12,000 Gates, 150-MHz Performance >9,000 Customers Using Products TTL LIB EP1200 EPB1400 7032V MAX 9000 ALTR IPO FLEX 8000 ACCESS EDA MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B Simple Control Logic SOPC Complex Logic System...
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This note was uploaded on 01/05/2012 for the course ECEN 212 taught by Professor Hamilton during the Fall '11 term at BYU.

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Altera - Copyright © 2003 Altera Corporation Copyright ©...

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