fm1final

fm1final - Simulation & synthesis of digital FM RECEIVER...

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Simulation & synthesis of digital FM RECEIVER USING VHDL 1 01/05/12 Digital FM Receiver
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Contents Problem definition Design flow Tools used Block Diagram Phase Detector Loop Filter NCO FIR Filter Simulation result FPGA Implementation Advantages Application Conclusion 2 01/05/12 Digital FM Receiver
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Problem definition The present work aims at the implementation o and analysis of digital FM receiver for FPGA Design specifications : Input frequency range: 88-108MHZ Input signal: 8 bits Output signal: 12 bits 3 01/05/12 Digital FM Receiver
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Design Flow 4 01/05/12 Digital FM Receiver
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Synthesis 5 01/05/12 Digital FM Receiver
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6 For simulation--------------------- Modelsim SE 6.3f For synthesis----------------------- Xilinx ISE 8.2i Hardware used-------------------- Spartan 3E Tools Used 01/05/12 Digital FM Receiver
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Spartan 3E 7 01/05/12 Digital FM Receiver
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Target 8 01/05/12 Digital FM Receiver
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Block Diagram 9 01/05/12 Digital FM Receiver
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Complete Block Diagram 10 01/05/12 Digital FM Receiver
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Phase Detector Detects phase error between input signal and output signal from NCO. Input signal
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This note was uploaded on 01/05/2012 for the course ECEN 212 taught by Professor Hamilton during the Fall '11 term at BYU.

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fm1final - Simulation & synthesis of digital FM RECEIVER...

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