LogicDevicesAndArchitecture

LogicDevicesAndArchitecture - Programmable Logic Devices...

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Unformatted text preview: Programmable Logic Devices and Architectures: A Nano-Course R. Katz Grunt Engineer NASA What We Will Cover • Various programmable logic types • Device architectures • Device performance • Packaging • Reliability • Some radiation considerations • Lessons learned What You Will Not Learn You will not learn much. This course is only a brief introduction to key concepts and issues, not a comprehensive and in-depth tutorial. Because of time limitations, sections have been either scaled back or eliminated. References References are available for most slides • Original work – available on http://rk.gsfc.nasa.gov • Manufacturers’ data sheets, application notes • Papers and reports – Many from MAPLD 1998, 1999, 2000 • Standard logic design textbooks Lessons Learned (1) Barto's Law : Every circuit is considered guilty until proven innocent. Lessons Learned (2) Launched: March 4, 1999 Failed: March 4, 1999 Applications Some Application Types • Existing SSI/MSI Integration • Obsolete/"Non-Space-Qualified" Component Replacement • Bus Controllers/Interfaces • Memory Controller/Scrubber • High-Performance DSP • Processors • Systems on Chip • Many Other Digital Circuits SSI/MSI Logic Integration Non-Space Qual Microcontroller Complex System-on-Chip SSTL Core ESA Core Debug CAN Network >100Mbps 170Mbyte Microdrive TX TC SP 1M*64 SRAM CAN BUS LVDS RX2 RX1 RX0 Linear Regulator POR +3.3V EDAC DECDED ROM LUT Bootstrap AMBA AHB CAN Interface AMBA AHB LEON Sparc V8 CORDIC Coprocessor AMBA AHB AMBA AHB HDLC TX Controller AMBA AHB HDLC RX Controller FIFO AMBA AHB HDLC RX Controller FIFO AMBA AHB HDLC RX Controller FIFO System Bus CF+ I/F True IDE FIFO Parallel Port Interface UART AMBA AHB PIO FIFO AMBA AHB +2.5V +3.3V CLK CLK CLK CLK Programmable Elements Overview • Antifuse – ONO and Metal-to-Metal (M2M) – Construction – Resistance • SRAM – Structure – Quantity • EEPROM/Flash • Ferroelectric Memory • Summary of Properties Antifuse Technology ONO Antifuse (Actel) Poly/ONO/N++ Heavy As doped Poly/N++ Thickness controlled by CVD nitride Programs ~ 18V Typical Toxono ~ 85 Å Hardened Toxono ~ 95 Å R = 200 - 500 ohms thermal oxide CVD nitride thermal oxide FOX N++ Polysilicon ONO Metal-to-Metal Antifuse (Actel, UTMC, Quicklogic) ‘Pancake’ Stack Between Metal Layers Used in 3.3V Operation in Sea Of Gates FPGA Other devices (as shown later) Program at ~ 10V Typical thickness ~ 500 - 1000 Å R = 20 - 100 ohms Metal - 3 Top Electrode Amorphous Silicon Dielectric (optional) Metal - 2 Bottom Electrode Antifuse Cross-Sections Amorphous Silicon (Vialink) ONO (Act 1) M2M = Metal-to-metal M2M Antifuse in Multi-layer Metal Process SX, SX-A, and SX-S Vialink Programmed Antifuse Resistance Distributions The resistance of programmed antifuses is stable with temperature, varying less than 15 percent per 100°C. SRAM Switch Technology Read or Write Data Configuration Memory Cell Routing Connections Summary of Current Technology...
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This note was uploaded on 01/05/2012 for the course ECEN 212 taught by Professor Hamilton during the Fall '11 term at BYU.

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LogicDevicesAndArchitecture - Programmable Logic Devices...

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