week4 - Week 4 I/O Ports and Their Programming Chapter 4 1...

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1 Week 4 I/O Ports and Their Programming Chapter 4
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2 8051 Pin diagram ± Figure 4-1. 8051 Pin Diagram ± The 8051 family members all have 40 pins. ² Vcc, GND, XTAL1, XTAL2,. .. (See Chapter 8). ² I/O port pins • The four ports: Port 0, Port 1, Port 2, and Port 3 • Usually we call them as P0, P1, P2, and P3. • Each port uses 8 pins.
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3 I/O Port Pins ± The 8051 has four I/O ports ² Port 0 pins 32-39 P0.0 to P0.7 ² Port 1 pins 1-8 P1.0 to P1.7 ² Port 2 pins 21-28 P2.0 to P2.7 ² Port 3 pins 10-17 P3.0 to P3.7 ² Each port has 8 pins . • Named P0.X , P1.X, P2.X, P3.X X=0,1,. ..,7 • P0.0 is the bit 0 (LSB) of P0 • P0.7 is the bit 7 (MSB) of P0 • These 8 bits form a byte. • Note that 8 pins of port can work independently. ± Each port can be used as input or output ( bi- directional ).
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4 Port P1 DQ Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB1 TB2 G D S
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5 Port pins ± Each pin of I/O ports ² Internal CPU bus communicates with CPU ² A D latch stores the value of this pin • D latch is controlled by “Write to latch” – Write to latch 1: write data into the D latch ² Two Tri-state buffers • TB1: controlled by “Read pin” – Read pin = 1 (TB1=1) read the data present at the pin • TB2: controlled by “Read latch” – Read latch=1 (TB2=1) read value from internal latch ² A transistor M gate • Gate = 0, output = 1 • Gate = 1, output = 0
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6 Writing 1 to output pin P1.X
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7 Writing 0 to output pin P1.X
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8 Reading High at Input Pin
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9 Reading Low at the Input Pin 2.MOV A,P1 External pin=Low
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10 Never connect direct Vcc to Port Pins
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11 Ways a) b) c)
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12 Reading the Latch ± ANL P1,A ± The read latch activates TB2 ± This data is ANDed with register A ± The result is overwritten to the latch
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13 Other Pins ± P1, P2, and P3 have internal pull-up resisters. ² P1, P2, and P3 are not open drain. ± P0 has no internal pull-up resistors and does not connect to Vcc inside the 8051. ² P0 is open drain . ² Compare the figures of P1.X and P0.X ± However, for a programmer, it is the same to program P0,P1,P2, and P3. ± All the ports, upon a RESET, receive a FFh
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14 P0 Structure
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15 P0 Structure ± P0 is an open drain. The reason is to multiplex address and data.
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This note was uploaded on 01/09/2012 for the course CS cs464 at Bilkent University.

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week4 - Week 4 I/O Ports and Their Programming Chapter 4 1...

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